diff options
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 17 |
4 files changed, 19 insertions, 12 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index f923a47db4..d923377b89 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -22,8 +22,8 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE -#define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE -#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_STACK_SLUSH +#define CacheSizeBSPStack CONFIG_DCACHE_BSP_TOP_STACK_SIZE +#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_TOP_STACK_SLUSH /* For CAR with Fam10h. */ #define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 50ed657f42..aa8222bc9d 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -131,9 +131,9 @@ asmlinkage void *post_cache_as_ram(void) * boundary during romstage execution */ volatile uint32_t *lower_stack_boundary; - lower_stack_boundary = - (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - - CONFIG_DCACHE_BSP_STACK_SIZE); + lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - + CONFIG_DCACHE_BSP_TOP_STACK_SIZE); + if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 1039a8d6ae..e9ee855209 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -37,11 +37,11 @@ config DCACHE_RAM_SIZE hex default 0x0c000 -config DCACHE_BSP_STACK_SIZE +config DCACHE_BSP_TOP_STACK_SIZE hex default 0x4000 -config DCACHE_BSP_STACK_SLUSH +config DCACHE_BSP_TOP_STACK_SLUSH hex default 0x4000 if USE_LARGE_DCACHE default 0x1000 diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index f416d9ccdb..eebbc48a0c 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -379,12 +379,19 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) uint8_t fam15_bsp_core1_apicid; struct node_core_id id; - /* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */ + /* Please refer to the calculations and explaination in cache_as_ram.inc + * before modifying these values */ uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE; - uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH; - uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; - uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size; - void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); + uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_TOP_STACK_SIZE + + CONFIG_DCACHE_BSP_TOP_STACK_SLUSH; + uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE; + uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - + max_bsp_stack_region_size; + + void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - + max_ap_stack_region_size); + if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) printk(BIOS_WARNING, "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", |