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-rw-r--r--src/cpu/amd/quadcore/Makefile.inc1
-rw-r--r--src/cpu/amd/quadcore/amd_sibling.c118
-rw-r--r--src/cpu/amd/quadcore/quadcore.c146
-rw-r--r--src/cpu/amd/quadcore/quadcore_id.c152
4 files changed, 0 insertions, 417 deletions
diff --git a/src/cpu/amd/quadcore/Makefile.inc b/src/cpu/amd/quadcore/Makefile.inc
deleted file mode 100644
index c390b4e295..0000000000
--- a/src/cpu/amd/quadcore/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-ramstage-y += amd_sibling.c
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
deleted file mode 100644
index ac637ff817..0000000000
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/lapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <smp/spinlock.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-
-extern struct device *get_node_pci(u32 nodeid, u32 fn);
-
-#if 0
-static int first_time = 1;
-#endif
-
-#include "quadcore_id.c"
-
-static u32 get_max_siblings(u32 nodes)
-{
- struct device *dev;
- u32 nodeid;
- u32 siblings = 0;
-
- //get max siblings from all the nodes
- for (nodeid = 0; nodeid < nodes; nodeid++) {
- int j;
- dev = get_node_pci(nodeid, 3);
- j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
- if (siblings < j)
- siblings = j;
- }
-
- return siblings;
-}
-
-
-static void enable_apic_ext_id(u32 nodes)
-{
- struct device *dev;
- u32 nodeid;
-
- //enable APIC_EXIT_ID all the nodes
- for (nodeid = 0; nodeid < nodes; nodeid++) {
- u32 val;
- dev = get_node_pci(nodeid, 0);
- val = pci_read_config32(dev, 0x68);
- val |= (1 << 17)|(1 << 18);
- pci_write_config32(dev, 0x68, val);
- }
-}
-
-
-u32 get_apicid_base(u32 ioapic_num)
-{
- u32 apicid_base;
- u32 siblings;
- u32 nb_cfg_54;
-
- u32 disable_siblings = !CONFIG(LOGICAL_CPUS);
-
- get_option(&disable_siblings, "multi_core");
-
- siblings = get_max_siblings(sysconf.nodes);
-
- if (sysconf.bsp_apicid > 0) {
- // IOAPIC could start from 0
- return 0;
- } else if (sysconf.enabled_apic_ext_id) {
- // enabled ext id but bsp = 0
- return 1;
- }
-
- nb_cfg_54 = read_nb_cfg_54();
-
-
- //Construct apicid_base
-
- if ((!disable_siblings) && (siblings > 0)) {
- /* for 8 way dual core, we will used up apicid 16:16, actually
- 16 is not allowed by current kernel and the kernel will try
- to get one that is small than 16 to make IOAPIC work. I don't
- know when the kernel can support 256 APIC id.
- (APIC_EXT_ID is enabled) */
-
- //4:10 for two way 8:12 for four way 16:16 for eight way
- //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes
- //for better consistency?
- apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes :
- 8 * siblings + sysconf.nodes;
-
- } else {
- apicid_base = sysconf.nodes;
- }
-
- if ((apicid_base+ioapic_num-1) > 0xf) {
- // We need to enable APIC EXT ID
- printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
- enable_apic_ext_id(sysconf.nodes);
- }
-
- return apicid_base;
-}
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
deleted file mode 100644
index 8125fb474f..0000000000
--- a/src/cpu/amd/quadcore/quadcore.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#if CONFIG(HAVE_OPTION_TABLE)
-#include "option_table.h"
-#endif
-
-#include "cpu/amd/quadcore/quadcore_id.c"
-
-u32 get_core_num_in_bsp(u32 nodeid)
-{
- u32 dword;
- if (is_fam15h()) {
- /* Family 15h moved CmpCap to F5x84 [7:0] */
- dword = pci_read_config32(NODE_PCI(nodeid, 5), 0x84);
- dword &= 0xff;
- } else {
- dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
- dword >>= 12;
- /* Bit 15 is CmpCap[2] since Revision D. */
- if ((cpuid_ecx(0x80000008) & 0xff) > 3)
- dword = ((dword & 8) >> 1) | (dword & 3);
- else
- dword &= 3;
- }
- return dword;
-}
-
-u8 set_apicid_cpuid_lo(void)
-{
- // set the NB_CFG[54]=1; why the OS will be happy with that ???
- msr_t msr;
- msr = rdmsr(NB_CFG_MSR);
- msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
- wrmsr(NB_CFG_MSR, msr);
-
- return 1;
-}
-
-void real_start_other_core(uint32_t nodeid, uint32_t cores)
-{
- ssize_t i;
- uint32_t dword;
-
- printk(BIOS_DEBUG,
- "Start other core - nodeid: %02x cores: %02x\n", nodeid, cores);
-
- /* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
- accesses and error logging to core0 */
- dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
- dword |= 1 << 30; /* SyncFloodOnDramAdrParErr=1 */
- dword |= 1 << 27; /* NbMcaToMstCpuEn=1 */
- dword |= 1 << 21; /* SyncFloodOnAnyUcErr=1 */
- dword |= 1 << 20; /* SyncFloodOnWDT=1 */
- dword |= 1 << 2; /* SyncFloodOnDramUcEcc=1 */
- pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
- if (is_fam15h()) {
- uint32_t core_activation_flags = 0;
- uint32_t active_cores = 0;
-
- /* Set PCI_DEV(0, 0x18+nodeid, 0),
- * 0x1dc bits 7:1 to start cores
- */
- dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x1dc);
- for (i = 1; i < cores + 1; i++)
- core_activation_flags |= 1 << i;
- /* Start the first core of each compute unit */
- active_cores |= core_activation_flags & 0x55;
- pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword
- | active_cores);
-
- /* Each core shares a single set of MTRR registers with
- * another core in the same compute unit, therefore, it
- * is important that one core in each CU starts in advance
- * of the other in order to avoid one core stomping all over
- * the other core's settings.
- */
-
- /* Wait for the first core of each compute unit to start... */
- for (i = 1; i < cores + 1; i++) {
- if (!(i & 0x1)) {
- uint32_t ap_apicid =
- get_boot_apic_id(nodeid, i);
- /* Timeout */
- wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP,
- F10_APSTATE_ASLEEP);
- }
- }
-
- /* Start the second core of each compute unit */
- active_cores |= core_activation_flags & 0xaa;
- pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword |
- active_cores);
- } else {
- // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
- dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
- dword |= 1 << 5;
- pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
-
- if (cores > 1) {
- dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
- for (i = 0; i < cores - 1; i++)
- dword |= 1 << i;
- pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
- }
- }
-}
-
-#if (!CONFIG(CPU_AMD_MODEL_10XXX))
-//it is running on core0 of node0
-static void start_other_cores(void)
-{
- u32 nodes;
- u32 nodeid;
-
- // disable multi_core
- if (read_option(multi_core, 0) != 0) {
- printk(BIOS_DEBUG, "Skip additional core init\n");
- return;
- }
-
- nodes = get_nodes();
-
- for (nodeid = 0; nodeid < nodes; nodeid++) {
- u32 cores = get_core_num_in_bsp(nodeid);
- printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n",
- nodeid, cores);
- if (cores > 0)
- real_start_other_core(nodeid, cores);
- }
-}
-#endif
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
deleted file mode 100644
index 7ec1bdb4f6..0000000000
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/cpu.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/multicore.h>
-#include <device/pci_ops.h>
-
-//called by bus_cpu_scan too
-u32 read_nb_cfg_54(void)
-{
- msr_t msr;
- msr = rdmsr(NB_CFG_MSR);
- return (msr.hi >> (54-32)) & 1;
-}
-
-u32 get_initial_apicid(void)
-{
- return (cpuid_ebx(1) >> 24) & 0xff;
-}
-
-/* Called by amd_siblings (ramstage) as well */
-struct node_core_id get_node_core_id(u32 nb_cfg_54)
-{
- struct node_core_id id;
- uint8_t apicid;
- uint8_t fam15h = 0;
- uint8_t rev_gte_d = 0;
- uint8_t dual_node = 0;
- uint32_t f3xe8;
- uint32_t family;
- uint32_t model;
-
-#if ENV_PCI_SIMPLE_DEVICE
- f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
-#else
- f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
-#endif
-
- family = model = cpuid_eax(0x80000001);
- model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
- if (family >= 0x6f) {
- /* Family 15h or later */
- fam15h = 1;
- nb_cfg_54 = 1;
- }
-
- if ((model >= 0x8) || fam15h)
- /* Revision D or later */
- rev_gte_d = 1;
-
- if (rev_gte_d)
- /* Check for dual node capability */
- if (f3xe8 & 0x20000000)
- dual_node = 1;
-
- /* Get the apicid via cpuid(1) ebx[31:24]
- * The apicid format varies based on processor revision
- */
- apicid = (cpuid_ebx(1) >> 24) & 0xff;
- if (nb_cfg_54) {
- if (fam15h && dual_node) {
- id.coreid = apicid & 0x1f;
- id.nodeid = (apicid & 0x60) >> 5;
- } else if (fam15h && !dual_node) {
- id.coreid = apicid & 0xf;
- id.nodeid = (apicid & 0x70) >> 4;
- } else if (rev_gte_d && dual_node) {
- id.coreid = apicid & 0xf;
- id.nodeid = (apicid & 0x30) >> 4;
- } else if (rev_gte_d && !dual_node) {
- id.coreid = apicid & 0x7;
- id.nodeid = (apicid & 0x38) >> 3;
- } else {
- id.coreid = apicid & 0x3;
- id.nodeid = (apicid & 0x1c) >> 2;
- }
- } else {
- if (rev_gte_d && dual_node) {
- id.coreid = (apicid & 0xf0) >> 4;
- id.nodeid = apicid & 0x3;
- } else if (rev_gte_d && !dual_node) {
- id.coreid = (apicid & 0xe0) >> 5;
- id.nodeid = apicid & 0x7;
- } else {
- id.coreid = (apicid & 0x60) >> 5;
- id.nodeid = apicid & 0x7;
- }
- }
- if (fam15h && dual_node) {
- /* coreboot expects each separate processor die to be on a
- * different nodeid.
- * Since the code above returns nodeid 0 even on
- * internal node 1 some fixup is needed...
- */
- uint32_t f5x84;
- uint8_t core_count;
-
-#if ENV_PCI_SIMPLE_DEVICE
- f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84);
-#else
- f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84);
-#endif
- core_count = (f5x84 & 0xff) + 1;
- id.nodeid = id.nodeid * 2;
- if (id.coreid >= core_count) {
- id.nodeid += 1;
- id.coreid = id.coreid - core_count;
- }
- } else if (rev_gte_d && dual_node) {
- /* coreboot expects each separate processor die to be on a
- * different nodeid.
- * Since the code above returns nodeid 0 even on
- * internal node 1 some fixup is needed...
- */
- uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) |
- ((f3xe8 & 0x00003000) >> 12)) + 1;
-
- id.nodeid = id.nodeid * 2;
- if (id.coreid >= core_count) {
- id.nodeid += 1;
- id.coreid = id.coreid - core_count;
- }
- }
-
- return id;
-}
-
-#ifdef UNUSED_CODE
-static u32 get_core_num(void)
-{
- return (cpuid_ecx(0x80000008) & 0xff);
-}
-#endif
-
-struct node_core_id get_node_core_id_x(void)
-{
- return get_node_core_id(read_nb_cfg_54());
-}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 09:27:24 +0000