diff options
Diffstat (limited to 'src/cpu/amd/pi/00670F00/fixme.c')
| -rw-r--r-- | src/cpu/amd/pi/00670F00/fixme.c | 50 |
1 files changed, 27 insertions, 23 deletions
diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index 9a38bd81ac..f892af87c9 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -25,37 +25,39 @@ void amd_initcpuio(void) AMD_CONFIG_PARAMS StdHeader; /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. + /* The platform BIOS needs to ensure the memory ranges of SB800 + * legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and + * ACPI) are set to non-posted regions. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + /* last address before processor local APIC at FEE00000 */ + PciData = 0x00FEDF00; PciData |= 1 << 7; /* set NP (non-posted) bit */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + /* lowest NP address is HPET at FED00000 */ + PciData = (0xFED00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -68,27 +70,29 @@ void amd_initmmio(void) AMD_CONFIG_PARAMS StdHeader; /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. + Set the MMIO Configuration Base Address and Bus Range onto MMIO + configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \ + (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + Set the NB_CFG MSR register. Enable CF8 extended config cycles. */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* For serial port */ PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ + 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); } |