diff options
Diffstat (limited to 'src/cpu/amd/model_lx')
| -rw-r--r-- | src/cpu/amd/model_lx/cpureginit.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/model_lx/msrinit.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c index 6e7de84c6a..bad98b51bf 100644 --- a/src/cpu/amd/model_lx/cpureginit.c +++ b/src/cpu/amd/model_lx/cpureginit.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee> * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com> * Copyright (C) 2007 Advanced Micro Devices, Inc. @@ -83,7 +83,7 @@ static const struct delay_controls { * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger) * is hooked up, then just don't do anything. This code was written by a master * of the Dark Arts at AMD and should not be modified in any way. - * + * * [1] (http://www.thefreedictionary.com/juju) * * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent). diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c index 6569338a2f..9c6e98e14c 100644 --- a/src/cpu/amd/model_lx/msrinit.c +++ b/src/cpu/amd/model_lx/msrinit.c @@ -45,7 +45,7 @@ static const msrinit_t msr_table[] = * of this extended memory will be to host the coreboot_ram stage at RAMBASE, * currently 1Mb. * These registers will be set to their correct value by the Northbridge init code. - * + * * WARNING: if coreboot_ram could not be loaded, these registers are probably * incorrectly set here. You may comment the following two lines and set RAMBASE * to 0x4000 to revert to the previous behavior for LX-boards. |