diff options
Diffstat (limited to 'src/cpu/amd/model_lx/msrinit.c')
| -rw-r--r-- | src/cpu/amd/model_lx/msrinit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c index 6569338a2f..9c6e98e14c 100644 --- a/src/cpu/amd/model_lx/msrinit.c +++ b/src/cpu/amd/model_lx/msrinit.c @@ -45,7 +45,7 @@ static const msrinit_t msr_table[] = * of this extended memory will be to host the coreboot_ram stage at RAMBASE, * currently 1Mb. * These registers will be set to their correct value by the Northbridge init code. - * + * * WARNING: if coreboot_ram could not be loaded, these registers are probably * incorrectly set here. You may comment the following two lines and set RAMBASE * to 0x4000 to revert to the previous behavior for LX-boards. |