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path: root/src/cpu/amd/model_gx2/cpureginit.c
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Diffstat (limited to 'src/cpu/amd/model_gx2/cpureginit.c')
-rw-r--r--src/cpu/amd/model_gx2/cpureginit.c205
1 files changed, 110 insertions, 95 deletions
diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index a1f55fe762..f2802b67ca 100644
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -9,8 +9,7 @@
/* **/
/* ***************************************************************************/
static void
-BIST(void)
-{
+BIST(void){
int msrnum;
msr_t msr;
@@ -25,8 +24,8 @@ BIST(void)
msrnum = CPU_DM_BIST;
wrmsr(msrnum, msr);
- outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
+ outb(POST_CPU_DM_BIST_FAILURE , 0x80); /* 0x29*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
msr.lo &= 0x0F3FF0000;
if (msr.lo != 0xfeff0000)
goto BISTFail;
@@ -42,115 +41,108 @@ BIST(void)
msrnum = CPU_FP_UROM_BIST;
wrmsr(msrnum, msr);
- outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
- inb(0x80); /* IO delay*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
+ outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
+ inb(0x80); /* IO delay*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
while ((msr.lo&0x884) != 0x884)
- msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
+ msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
if ((msr.lo&0x642) != 0x642)
goto BISTFail;
- msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
+
+ msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
msrnum = CPU_FP_UROM_BIST;
wrmsr(msrnum, msr);
+
/* BTB*/
msr.lo = 0x000000303;
msr.hi = 0x000000000;
msrnum = CPU_PF_BTBRMA_BIST;
wrmsr(msrnum, msr);
- outb(POST_CPU_BTB_BIST_FAILURE, 0x80); /* 0x8A*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
+ outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
if ((msr.lo & 0x3030) != 0x3030)
goto BISTFail;
return;
+
BISTFail:
print_err("BIST failed!\n");
while(1);
}
-
-void BTM_enable(void)
-{
- int msrnum;
- msr_t msr;
- /* Set Diagnostic Mode */
- msrnum = CPU_GLD_MSR_DIAG;
- msr.hi = 0;
- msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
- wrmsr(msrnum, msr);
-
- /* Set up GLCP to grab BTM data.*/
- msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
- msr.hi = 0x0;
- msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
- wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
-
- /* ;Turn off debug clock*/
- msrnum = 0x04C000016; /* DBG_CLK_CTL*/
- msr.lo = 0x00; /* No clock*/
- msr.hi = 0x00;
- wrmsr(msrnum, msr);
-
- /* ;Set debug clock to CPU*/
- msrnum = 0x04C000016; /* DBG_CLK_CTL*/
- msr.lo = 0x01; /* CPU CLOCK*/
- msr.hi = 0x00;
- wrmsr(msrnum, msr);
-
- /* ;Set fifo ctl to BTM bits wide*/
- msrnum = 0x04C00005E; /* FIFO_CTL*/
- msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit,
- * 01= 32 bit, 00 = 16bit),
- * Bit [23:21] are position (100 = CPU downto0)*/
- wrmsr(msrnum, msr); /* */
- /* Bit [19] sets it up in slow data mode.*/
-
- /* ;enable fifo loading - BTM sizing will constrain*/
- /* ; only valid BTM packets to load - this action should always be on*/
- msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
- msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
- msr.hi = 0x000000000; /* */
- wrmsr(msrnum, msr);
-
- /* ;start storing diag data in the fifo*/
- msrnum = 0x04C00005F; /* DIAG CTL*/
- msr.lo = 0x080000000; /* enable actions*/
- msr.hi = 0x000000000;
- wrmsr(msrnum, msr);
-
- /* Set up delay on data lines, so that the hold time*/
- /* is 1 ns.*/
- msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
- msr.lo = 0x082b5ad68;
- msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
- wrmsr(msrnum, msr);
-
- /* Set up DF to output diag information on DF pins.*/
- msrnum = DF_GLD_MSR_MASTER_CONF;
- msr.lo = 0x0220;
- msr.hi = 0;
- wrmsr(msrnum, msr);
-
- msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
- msr.hi = 0x0;
- msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
- wrmsr(msrnum, msr);
- /* end of code for BTM */
-}
-
/* ***************************************************************************/
/* * cpuRegInit*/
/* ***************************************************************************/
void
-cpuRegInit (void)
-{
+cpuRegInit (void){
int msrnum;
msr_t msr;
/* Turn on BTM for early debug based on setup. */
/*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/
{
- BTM_enable();
+ /* Set Diagnostic Mode */
+ msrnum = CPU_GLD_MSR_DIAG;
+ msr.hi = 0;
+ msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
+ wrmsr(msrnum, msr);
+
+ /* Set up GLCP to grab BTM data.*/
+ msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
+ msr.hi = 0x0;
+ msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
+ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
+
+ /* ;Turn off debug clock*/
+ msrnum = 0x04C000016; /* DBG_CLK_CTL*/
+ msr.lo = 0x00; /* No clock*/
+ msr.hi = 0x00;
+ wrmsr(msrnum, msr);
+
+ /* ;Set debug clock to CPU*/
+ msrnum = 0x04C000016; /* DBG_CLK_CTL*/
+ msr.lo = 0x01; /* CPU CLOCK*/
+ msr.hi = 0x00;
+ wrmsr(msrnum, msr);
+
+ /* ;Set fifo ctl to BTM bits wide*/
+ msrnum = 0x04C00005E; /* FIFO_CTL*/
+ msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
+ wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
+ /* Bit [19] sets it up in slow data mode.*/
+
+ /* ;enable fifo loading - BTM sizing will constrain*/
+ /* ; only valid BTM packets to load - this action should always be on*/
+
+ msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
+ msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
+ msr.hi = 0x000000000; /* */
+ wrmsr(msrnum, msr);
+
+ /* ;start storing diag data in the fifo*/
+ msrnum = 0x04C00005F; /* DIAG CTL*/
+ msr.lo = 0x080000000; /* enable actions*/
+ msr.hi = 0x000000000;
+ wrmsr(msrnum, msr);
+
+ /* Set up delay on data lines, so that the hold time*/
+ /* is 1 ns.*/
+ msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
+ msr.lo = 0x082b5ad68;
+ msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
+ wrmsr(msrnum, msr);
+
+ /* Set up DF to output diag information on DF pins.*/
+ msrnum = DF_GLD_MSR_MASTER_CONF;
+ msr.lo = 0x0220;
+ msr.hi = 0;
+ wrmsr(msrnum, msr);
+
+ msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
+ msr.hi = 0x0;
+ msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
+ wrmsr(msrnum, msr);
+ /* end of code for BTM */
}
/* Enable Suspend on Halt*/
@@ -172,32 +164,49 @@ cpuRegInit (void)
msr.lo = 0x00000603C;
wrmsr(msrnum, msr);
- /* Enable CIS mode C */
+
+/* Only do this if we are building for 5535*/
+/* */
+/* FooGlue Setup*/
+/* */
+#if 1
+ /* Enable CIS mode B in FooGlue*/
msrnum = MSR_FG + 0x10;
msr = rdmsr(msrnum);
msr.lo &= ~3;
- msr.lo |= 2;
+ msr.lo |= 2; /* ModeB*/
wrmsr(msrnum, msr);
+#endif
- /* Disable DOT PLL. Graphics init will enable it if needed.*/
+/* */
+/* Disable DOT PLL. Graphics init will enable it if needed.*/
+/* */
msrnum = GLCP_DOTPLL;
msr = rdmsr(msrnum);
msr.lo |= DOTPPL_LOWER_PD_SET;
wrmsr(msrnum, msr);
- /* Enable RSDC and other SMM instructions */
+/* */
+/* Enable RSDC*/
+/* */
msrnum = 0x1301 ;
msr = rdmsr(msrnum);
msr.lo |= 0x08;
wrmsr(msrnum, msr);
- /* BIST*/
+
+/* */
+/* BIST*/
+/* */
/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
{
- //BIST();
+// BIST();
}
- /* Enable BTB*/
+
+/* */
+/* Enable BTB*/
+/* */
/* I hate to put this check here but it doesn't really work in cpubug.asm*/
msrnum = MSR_GLCP+0x17;
msr = rdmsr(msrnum);
@@ -208,7 +217,9 @@ cpuRegInit (void)
wrmsr(msrnum, msr);
}
- /* FPU impercise exceptions bit*/
+/* */
+/* FPU impercise exceptions bit*/
+/* */
/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
{
msrnum = CPU_FPU_MSR_MODE;
@@ -217,7 +228,9 @@ cpuRegInit (void)
wrmsr(msrnum, msr);
}
- /* Cache Overides*/
+/* */
+/* Cache Overides*/
+/* */
/* Allow NVRam to override DM Setup*/
/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
{
@@ -237,6 +250,9 @@ cpuRegInit (void)
}
}
+
+
+
/* ***************************************************************************/
/* **/
/* * MTestPinCheckBX*/
@@ -246,8 +262,7 @@ cpuRegInit (void)
/* **/
/* ***************************************************************************/
static void
-MTestPinCheckBX (void)
-{
+MTestPinCheckBX (void){
int msrnum;
msr_t msr;
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 05:05:15 +0000