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-rw-r--r--src/cpu/amd/model_fxx/init_cpus.c2
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_init.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 8968e7e0be..51e1b7c849 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -326,7 +326,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
apicid);
}
lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu
- set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
+ set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
#if CONFIG_K8_REV_F_SUPPORT
#if CONFIG_MEM_TRAIN_SEQ == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo,
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index b1e599acb1..cf0b08a04c 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -173,12 +173,12 @@ static void set_init_ecc_mtrrs(void)
wrmsr(MTRR_PHYS_MASK(i), zero);
}
- /* Write back cache the first 1MB */
+ /* Write back cache from 0x0 to CACHE_TMP_RAMTOP. */
msr.hi = 0x00000000;
msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
wrmsr(MTRR_PHYS_BASE(0), msr);
msr.hi = 0x000000ff;
- msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
+ msr.lo = ~((CACHE_TMP_RAMTOP) - 1) | 0x800;
wrmsr(MTRR_PHYS_MASK(0), msr);
/* Set the default type to write combining */