diff options
Diffstat (limited to 'src/cpu/amd/model_10xxx')
| -rw-r--r-- | src/cpu/amd/model_10xxx/defaults.h | 82 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/update_microcode.c | 2 |
2 files changed, 43 insertions, 41 deletions
diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h index a2ee0cac94..65290089f1 100644 --- a/src/cpu/amd/model_10xxx/defaults.h +++ b/src/cpu/amd/model_10xxx/defaults.h @@ -290,7 +290,7 @@ static const struct { /* errata 346 - Fam10 C2 * System software should set F3x188[22] to 1b. */ - { 3, 0x188, AMD_RB_C2, AMD_PTYPE_ALL, + { 3, 0x188, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, 0x00400000, 0x00400000 }, /* L3 Control Register */ @@ -317,82 +317,82 @@ static const struct { /* Errata 344 - Fam10 C2 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ - { 0x60, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x60, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x61, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x61, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x62, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x62, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x63, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x63, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x64, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x64, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x65, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x65, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x66, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x66, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x67, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x67, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x68, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x68, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x70, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x70, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x71, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x71, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x72, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x72, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x73, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x73, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x74, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x74, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x75, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x75, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x76, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x76, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x77, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x77, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x78, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x78, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, /* Errata 354 - Fam10 C2 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */ - { 0x40, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x40, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x41, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x41, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x42, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x42, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x43, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x43, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x44, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x44, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x45, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x45, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x46, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x46, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x47, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x47, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x48, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x48, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x50, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x50, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x51, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x51, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x52, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x52, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x53, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x53, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x54, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x54, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x55, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x55, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x56, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x56, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x57, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x57, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x58, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x58, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, /* Errata 327 - Fam10 C2 @@ -400,15 +400,15 @@ static const struct { * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and * Link Phy Impedance Register[RttIndex] * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */ - { 0xC0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xC0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, - { 0xD0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xD0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, - { 0x520A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x520A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ - { 0x530A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x530A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index f996247d8d..ff38c65377 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -44,6 +44,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { * 00100F2Ah (DR-BA) 1020h 01000096h * 00100F22h (DR-B2) 1022h 01000095h * 00100F23h (DR-B3) 1022h 01000095h + * 00100F42h (RB-C2) 1041h 01000086h * 00100F62h (DA-C2) 1062h 0100009Fh */ @@ -67,6 +68,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) { 0x100f2A, 0x1020, 0x100f22, 0x1022, 0x100f23, 0x1022, + 0x100f42, 0x1041, 0x100f62, 0x1062, }; |