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-rw-r--r--src/cpu/amd/model_10xxx/Kconfig4
-rw-r--r--src/cpu/amd/model_10xxx/init_cpus.c5
2 files changed, 8 insertions, 1 deletions
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 4b5cdedaa1..ebd282a5ca 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -34,6 +34,10 @@ config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
+config DCACHE_BSP_STACK_SLUSH
+ hex
+ default 0x1000
+
config DCACHE_AP_STACK_SIZE
hex
default 0x400
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 7e79307c89..4c72848986 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -250,8 +250,11 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
u32 apicid;
struct node_core_id id;
+ /* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */
uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE;
- uint32_t bsp_stack_region_lower_boundary = CONFIG_DCACHE_RAM_BASE + (CONFIG_DCACHE_RAM_SIZE / 2);
+ uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH;
+ uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE;
+ uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size;
void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size);
if (((void*)(sysinfo + 1)) > lower_stack_region_boundary)
printk(BIOS_WARNING,