diff options
Diffstat (limited to 'src/cpu/amd/dualcore')
| -rw-r--r-- | src/cpu/amd/dualcore/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/cpu/amd/dualcore/amd_sibling.c | 130 | ||||
| -rw-r--r-- | src/cpu/amd/dualcore/dualcore.c | 76 | ||||
| -rw-r--r-- | src/cpu/amd/dualcore/dualcore_id.c | 67 |
4 files changed, 0 insertions, 275 deletions
diff --git a/src/cpu/amd/dualcore/Makefile.inc b/src/cpu/amd/dualcore/Makefile.inc deleted file mode 100644 index f9571d1c3c..0000000000 --- a/src/cpu/amd/dualcore/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -# This is a leaf Makefile, no conditionals. If it is included it will be used. -ramstage-y += amd_sibling.c diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c deleted file mode 100644 index 9a450a52d8..0000000000 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * 2004.12 yhlu add dual core support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/multicore.h> -#include <device/device.h> -#include <device/pci.h> -#include <pc80/mc146818rtc.h> -#include <smp/spinlock.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/model_fxx_rev.h> -#include <cpu/amd/amdk8_sysconf.h> - -static int disable_siblings = !CONFIG_LOGICAL_CPUS; - -#include "dualcore_id.c" - -static int get_max_siblings(int nodes) -{ - struct device *dev; - int nodeid; - int siblings=0; - - //get max siblings from all the nodes - for (nodeid=0; nodeid<nodes; nodeid++){ - int j; - dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3)); - j = (pci_read_config32(dev, 0xe8) >> 12) & 3; - if (siblings < j) { - siblings = j; - } - } - - return siblings; -} - -static void enable_apic_ext_id(int nodes) -{ - struct device *dev; - int nodeid; - - //enable APIC_EXIT_ID all the nodes - for (nodeid=0; nodeid<nodes; nodeid++){ - uint32_t val; - dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); - val = pci_read_config32(dev, 0x68); - val |= (1 << 17)|(1 << 18); - pci_write_config32(dev, 0x68, val); - } -} - - -unsigned get_apicid_base(unsigned ioapic_num) -{ - struct device *dev; - int nodes; - unsigned apicid_base; - int siblings; - unsigned nb_cfg_54; - int bsp_apic_id = lapicid(); // bsp apicid - - get_option(&disable_siblings, "multi_core"); - - //get the nodes number - dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); - nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; - - siblings = get_max_siblings(nodes); - - if (bsp_apic_id > 0) { // IOAPIC could start from 0 - return 0; - } else if (pci_read_config32(dev, 0x68) & ( (1 << 17) | (1 << 18)) ) { // enabled ext id but bsp = 0 - return 1; - } - - nb_cfg_54 = read_nb_cfg_54(); - -#if 0 - //it is for all e0 single core and nc_cfg_54 low is set, but in the romstage.c stage we do not set that bit for it. - if (nb_cfg_54 && (!disable_siblings) && (siblings == 0)) { - //we need to check if e0 single core is there - int i; - for (i=0; i<nodes; i++) { - if (is_e0_later_in_bsp(i)) { - siblings = 1; - break; - } - } - } -#endif - - //Construct apicid_base - - if ((!disable_siblings) && (siblings>0) ) { - /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel - and the kernel will try to get one that is small than 16 to make IOAPIC work. - I don't know when the kernel can support 256 APIC id. (APIC_EXT_ID is enabled) */ - - //4:10 for two way 8:12 for four way 16:16 for eight way - //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency? - apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes; - - } - else { - apicid_base = nodes; - } - - if ((apicid_base+ioapic_num-1)>0xf) { - // We need to enable APIC EXT ID - printk(BIOS_INFO, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for IOAPIC\n"); - enable_apic_ext_id(nodes); - } - - return apicid_base; -} diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c deleted file mode 100644 index a388354e9e..0000000000 --- a/src/cpu/amd/dualcore/dualcore.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Yinghai Lu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "cpu/amd/dualcore/dualcore_id.c" -#include <pc80/mc146818rtc.h> -#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) -#include "option_table.h" -#endif - -static inline unsigned get_core_num_in_bsp(unsigned nodeid) -{ - uint32_t dword; - dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0xe8); - dword >>= 12; - dword &= 3; - return dword; -} - -static inline uint8_t set_apicid_cpuid_lo(void) -{ -#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) - if (is_cpu_pre_e0()) return 0; // pre_e0 can not be set -#endif - - // set the NB_CFG[54]=1; why the OS will be happy with that ??? - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo - wrmsr(NB_CFG_MSR, msr); - - return 1; -} - -static inline void real_start_other_core(unsigned nodeid) -{ - uint32_t dword; - // set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0 - dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44); - dword |= 1 << 27; // NbMcaToMstCpuEn bit - pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword); - // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1 - dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68); - dword |= 1 << 5; - pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword); -} - -//it is running on core0 of node0 -static inline void start_other_cores(void) -{ - unsigned nodes; - unsigned nodeid; - - if (read_option(multi_core, 0)) { - return; // disable multi_core - } - - nodes = get_nodes(); - - for (nodeid=0; nodeid<nodes; nodeid++) { - if ( get_core_num_in_bsp(nodeid) > 0) { - real_start_other_core(nodeid); - } - } -} diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c deleted file mode 100644 index e7af552dcb..0000000000 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Yinghai Lu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <cpu/amd/multicore.h> -#ifdef __PRE_RAM__ -#include <cpu/amd/msr.h> -#endif - -//called by bus_cpu_scan too -unsigned int read_nb_cfg_54(void) -{ - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - return ( ( msr.hi >> (54-32)) & 1); -} - -u32 get_initial_apicid(void) -{ - return ((cpuid_ebx(1) >> 24) & 0xf); -} - -//called by amd_siblings too -#define CORE_ID_BIT 1 -#define NODE_ID_BIT 3 -struct node_core_id get_node_core_id(unsigned nb_cfg_54) -{ - struct node_core_id id; - // get the apicid via cpuid(1) ebx[27:24] - if ( nb_cfg_54) { - // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] - id.coreid = (cpuid_ebx(1) >> 24) & 0xf; - id.nodeid = (id.coreid>>CORE_ID_BIT); - id.coreid &= ((1 << CORE_ID_BIT)-1); - } - else - { - // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27] - id.nodeid = (cpuid_ebx(1) >> 24) & 0xf; - id.coreid = (id.nodeid>>NODE_ID_BIT); - id.nodeid &= ((1 << NODE_ID_BIT)-1); - } - return id; -} - -static inline unsigned get_core_num(void) -{ - return (cpuid_ecx(0x80000008) & 0xff); -} - -struct node_core_id get_node_core_id_x(void) -{ - - return get_node_core_id(read_nb_cfg_54()); // for pre_e0() nb_cfg_54 always be 0 -} |