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-rw-r--r--src/cpu/amd/car/cache_as_ram.inc3
-rw-r--r--src/cpu/amd/car/disable_cache_as_ram.c4
2 files changed, 5 insertions, 2 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 4625da1ca0..18a19fc030 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -19,6 +19,7 @@
*/
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
@@ -320,7 +321,7 @@ wbcache_post_fam10_setup:
/* Enable cache. */
movl %cr0, %eax
- andl $(~((1 << 30) | (1 << 29))), %eax
+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0
jmp_if_k8(fam10_end_part1)
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index 0f91154824..a48a39c6ab 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -21,12 +21,14 @@
* be warned, this file will be used other cores and core 0 / node 0
*/
+#include <cpu/x86/cache.h>
+
static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{
msr_t msr;
/* disable cache */
- write_cr0(read_cr0() | (1 << 30));
+ write_cr0(read_cr0() | CR0_CacheDisable);
msr.lo = 0;
msr.hi = 0;