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Diffstat (limited to 'src/cpu/amd/agesa')
-rw-r--r--src/cpu/amd/agesa/cache_as_ram.inc2
-rw-r--r--src/cpu/amd/agesa/cache_as_ram_legacy.inc2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 857873a682..8038177c7c 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -40,7 +40,7 @@ cache_as_ram_setup:
/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
movl %cr4, %eax
- orl $(3<<9), %eax
+ orl $(3 << 9), %eax
movl %eax, %cr4
post_code(0xa1)
diff --git a/src/cpu/amd/agesa/cache_as_ram_legacy.inc b/src/cpu/amd/agesa/cache_as_ram_legacy.inc
index c0a69ec74a..55480070c9 100644
--- a/src/cpu/amd/agesa/cache_as_ram_legacy.inc
+++ b/src/cpu/amd/agesa/cache_as_ram_legacy.inc
@@ -43,7 +43,7 @@ cache_as_ram_setup:
/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
movl %cr4, %eax
- orl $(3<<9), %eax
+ orl $(3 << 9), %eax
movl %eax, %cr4
/* Get the cpu_init_detected */