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path: root/src/cpu/amd/agesa/family15tn/model_15_init.c
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Diffstat (limited to 'src/cpu/amd/agesa/family15tn/model_15_init.c')
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 8ae184e78d..fdcb9a2332 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -35,6 +35,7 @@ static void model_15_init(struct device *dev)
u8 i;
msr_t msr;
+ int num_banks;
int msrno;
unsigned int cpu_idx;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
@@ -72,9 +73,11 @@ static void model_15_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0; i < 6; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */