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-rw-r--r--src/cpu/amd/agesa/family15rl/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family15rl/romstage.c91
2 files changed, 92 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc
index 98a7050c21..4fcaff7405 100644
--- a/src/cpu/amd/agesa/family15rl/Makefile.inc
+++ b/src/cpu/amd/agesa/family15rl/Makefile.inc
@@ -14,6 +14,7 @@
#
romstage-y += fixme.c
+romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c
new file mode 100644
index 0000000000..e0a434c8f4
--- /dev/null
+++ b/src/cpu/amd/agesa/family15rl/romstage.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/car.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ struct sysinfo *cb = NULL;
+ u32 val;
+
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ board_BeforeAgesa(cb);
+
+ post_code(0x31);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ agesawrapper_amdinitreset();
+
+ post_code(0x39);
+ agesawrapper_amdinitearly();
+
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ agesawrapper_amdinitpost();
+
+ post_code(0x41);
+ agesawrapper_amdinitenv();
+
+ disable_cache_as_ram();
+ } else {
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ agesawrapper_amdinitresume();
+
+ amd_initcpuio();
+ agesawrapper_amds3laterestore();
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ post_code(0x50);
+ copy_and_run();
+}
+