aboutsummaryrefslogtreecommitdiff
path: root/src/cpu/amd/agesa/family14/fixme.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/amd/agesa/family14/fixme.c')
-rw-r--r--src/cpu/amd/agesa/family14/fixme.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index d1bd0a1d78..ab10e3a704 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -92,6 +92,12 @@ void amd_initmmio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;
+ LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
}
void amd_initenv(void)