diff options
Diffstat (limited to 'src/cpu/amd/agesa/Kconfig')
| -rw-r--r-- | src/cpu/amd/agesa/Kconfig | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index f21bf5467f..b1fde2dcf7 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -28,20 +28,10 @@ config CPU_AMD_AGESA select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG + select NO_FIXED_XIP_ROM_SIZE if CPU_AMD_AGESA -config XIP_ROM_SIZE - hex - default 0x100000 - help - Overwride the default write through caching size as 1M Bytes. - On some AMD platforms, one socket supports 2 or more kinds of - processor family, compiling several CPU families agesa code - will increase the romstage size. - In order to execute romstage in place on the flash ROM, - more space is required to be set as write through caching. - config UDELAY_LAPIC_FIXED_FSB int default 200 |