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Diffstat (limited to 'src/cpu/allwinner/a10')
-rw-r--r--src/cpu/allwinner/a10/clock.c12
-rw-r--r--src/cpu/allwinner/a10/gpio.c2
-rw-r--r--src/cpu/allwinner/a10/pinmux.c4
-rw-r--r--src/cpu/allwinner/a10/raminit.c28
-rw-r--r--src/cpu/allwinner/a10/timer.c6
-rw-r--r--src/cpu/allwinner/a10/twi.c14
-rw-r--r--src/cpu/allwinner/a10/uart.c12
7 files changed, 39 insertions, 39 deletions
diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
index a8e21514d3..e7984dd328 100644
--- a/src/cpu/allwinner/a10/clock.c
+++ b/src/cpu/allwinner/a10/clock.c
@@ -28,7 +28,7 @@ void a1x_periph_clock_enable(enum a1x_clken periph)
addr = (void *)A1X_CCM_BASE + (periph >> 5);
reg32 = read32(addr);
reg32 |= 1 << (periph & 0x1f);
- write32(reg32, addr);
+ writel(reg32, addr);
}
/**
@@ -44,7 +44,7 @@ void a1x_periph_clock_disable(enum a1x_clken periph)
addr = (void *)A1X_CCM_BASE + (periph >> 5);
reg32 = read32(addr);
reg32 &= ~(1 << (periph & 0x1f));
- write32(reg32, addr);
+ writel(reg32, addr);
}
/**
@@ -88,7 +88,7 @@ void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p)
reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) |
PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p));
reg32 |= PLL5_PLL_ENABLE;
- write32(reg32, &ccm->pll5_cfg);
+ writel(reg32, &ccm->pll5_cfg);
}
/**
@@ -166,7 +166,7 @@ static void cpu_clk_src_switch(u32 clksel_bits)
reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
reg32 &= ~CPU_CLK_SRC_MASK;
reg32 |= clksel_bits & CPU_CLK_SRC_MASK;
- write32(reg32, &ccm->cpu_ahb_apb0_cfg);
+ writel(reg32, &ccm->cpu_ahb_apb0_cfg);
}
static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
@@ -179,7 +179,7 @@ static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
reg32 |= ((axi - 1) << 0) & AXI_DIV_MASK;
reg32 |= (ahb_exp << 4) & AHB_DIV_MASK;
reg32 |= (apb0_exp << 8) & APB0_DIV_MASK;
- write32(reg32, &ccm->cpu_ahb_apb0_cfg);
+ writel(reg32, &ccm->cpu_ahb_apb0_cfg);
}
static void spin_delay(u32 loops)
@@ -262,7 +262,7 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
change_sys_divisors(axi, ahb_exp, apb0_exp);
/* Configure PLL1 at the desired frequency */
- write32(pll1_table[i].pll1_cfg, &ccm->pll1_cfg);
+ writel(pll1_table[i].pll1_cfg, &ccm->pll1_cfg);
spin_delay(8);
cpu_clk_src_switch(CPU_CLK_SRC_PLL1);
diff --git a/src/cpu/allwinner/a10/gpio.c b/src/cpu/allwinner/a10/gpio.c
index 5fca2d7c80..61f120d714 100644
--- a/src/cpu/allwinner/a10/gpio.c
+++ b/src/cpu/allwinner/a10/gpio.c
@@ -76,7 +76,7 @@ void gpio_write(u8 port, u32 val)
if ((port > GPS))
return;
- write32(val, &gpio->port[port].dat);
+ writel(val, &gpio->port[port].dat);
}
/**
diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c
index de87440d8f..d22647fc70 100644
--- a/src/cpu/allwinner/a10/pinmux.c
+++ b/src/cpu/allwinner/a10/pinmux.c
@@ -33,7 +33,7 @@ void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func)
reg32 = read32(&gpio->port[port].cfg[reg]);
reg32 &= ~(0xf << bit);
reg32 |= (pad_func & 0xf) << bit;
- write32(reg32, &gpio->port[port].cfg[reg]);
+ writel(reg32, &gpio->port[port].cfg[reg]);
}
/**
@@ -74,6 +74,6 @@ void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func)
reg32 &= ~(0xf << bit);
reg32 |= (pad_func & 0xf) << bit;
}
- write32(reg32, &gpio->port[port].cfg[reg]);
+ writel(reg32, &gpio->port[port].cfg[reg]);
}
}
diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c
index de24e03ec8..c1df4f427a 100644
--- a/src/cpu/allwinner/a10/raminit.c
+++ b/src/cpu/allwinner/a10/raminit.c
@@ -118,7 +118,7 @@ static void mctl_configure_hostport(void)
u32 i;
for (i = 0; i < 32; i++)
- write32(hpcr_value[i], &dram->hpcr[i]);
+ writel(hpcr_value[i], &dram->hpcr[i]);
}
static void mctl_setup_dram_clock(u32 clk)
@@ -333,9 +333,9 @@ static void dramc_set_autorefresh_cycle(u32 clk)
tmp_val = tmp_val * 9 - 200;
reg32 |= tmp_val << 8;
reg32 |= 0x8 << 24;
- write32(reg32, &dram->drr);
+ writel(reg32, &dram->drr);
} else {
- write32(0x0, &dram->drr);
+ writel(0x0, &dram->drr);
}
}
@@ -360,7 +360,7 @@ unsigned long dramc_init(struct dram_para *para)
a1x_gate_dram_clock_output();
/* select dram controller 1 */
- write32(DRAM_CSEL_MAGIC, &dram->csel);
+ writel(DRAM_CSEL_MAGIC, &dram->csel);
mctl_itm_disable();
mctl_enable_dll0(para->tpr3);
@@ -390,7 +390,7 @@ unsigned long dramc_init(struct dram_para *para)
reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
reg32 |= DRAM_DCR_CMD_RANK_ALL;
reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
- write32(reg32, &dram->dcr);
+ writel(reg32, &dram->dcr);
/* dram clock on */
a1x_ungate_dram_clock_output();
@@ -405,21 +405,21 @@ unsigned long dramc_init(struct dram_para *para)
reg32 = ((para->zq) >> 8) & 0xfffff;
reg32 |= ((para->zq) & 0xff) << 20;
reg32 |= (para->zq) & 0xf0000000;
- write32(reg32, &dram->zqcr0);
+ writel(reg32, &dram->zqcr0);
/* set I/O configure register */
reg32 = 0x00cc0000;
reg32 |= (para->odt_en) & 0x3;
reg32 |= ((para->odt_en) & 0x3) << 30;
- write32(reg32, &dram->iocr);
+ writel(reg32, &dram->iocr);
/* set refresh period */
dramc_set_autorefresh_cycle(para->clock);
/* set timing parameters */
- write32(para->tpr0, &dram->tpr0);
- write32(para->tpr1, &dram->tpr1);
- write32(para->tpr2, &dram->tpr2);
+ writel(para->tpr0, &dram->tpr0);
+ writel(para->tpr1, &dram->tpr1);
+ writel(para->tpr2, &dram->tpr2);
if (para->type == DRAM_MEMORY_TYPE_DDR3) {
reg32 = DRAM_MR_BURST_LENGTH(0x0);
@@ -430,11 +430,11 @@ unsigned long dramc_init(struct dram_para *para)
reg32 |= DRAM_MR_CAS_LAT(para->cas);
reg32 |= DRAM_MR_WRITE_RECOVERY(0x5);
}
- write32(reg32, &dram->mr);
+ writel(reg32, &dram->mr);
- write32(para->emr1, &dram->emr);
- write32(para->emr2, &dram->emr2);
- write32(para->emr3, &dram->emr3);
+ writel(para->emr1, &dram->emr);
+ writel(para->emr2, &dram->emr2);
+ writel(para->emr3, &dram->emr3);
/* set DQS window mode */
clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c
index 7d5d1419c3..2ff88f528d 100644
--- a/src/cpu/allwinner/a10/timer.c
+++ b/src/cpu/allwinner/a10/timer.c
@@ -24,13 +24,13 @@ void init_timer(void)
{
u32 reg32;
/* Load the timer rollover value */
- write32(0xffffffff, &tmr0->interval);
+ writel(0xffffffff, &tmr0->interval);
/* Configure the timer to run from 24MHz oscillator, no prescaler */
reg32 = TIMER_CTRL_PRESC_DIV_EXP(0);
reg32 |= TIMER_CTRL_CLK_SRC_OSC24M;
reg32 |= TIMER_CTRL_RELOAD;
reg32 |= TIMER_CTRL_TMR_EN;
- write32(reg32, &tmr0->ctrl);
+ writel(reg32, &tmr0->ctrl);
}
void udelay(unsigned usec)
@@ -61,6 +61,6 @@ void udelay(unsigned usec)
*/
u8 a1x_get_cpu_chip_revision(void)
{
- write32(0, &timer_module->cpu_cfg);
+ writel(0, &timer_module->cpu_cfg);
return (read32(&timer_module->cpu_cfg) >> 6) & 0x3;
}
diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c
index 2584126874..b5d9880847 100644
--- a/src/cpu/allwinner/a10/twi.c
+++ b/src/cpu/allwinner/a10/twi.c
@@ -42,7 +42,7 @@ static void configure_clock(struct a1x_twi *twi, u32 speed_hz)
/* Pre-divide the clock by 8 */
n = 3;
m = (apb_clk >> n) / speed_hz;
- write32(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk);
+ writel(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk);
}
void a1x_twi_init(u8 bus, u32 speed_hz)
@@ -53,9 +53,9 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
configure_clock(twi, speed_hz);
/* Enable the I²C bus */
- write32(TWI_CTL_BUS_EN, &twi->ctl);
+ writel(TWI_CTL_BUS_EN, &twi->ctl);
/* Issue soft reset */
- write32(1, &twi->reset);
+ writel(1, &twi->reset);
while (i-- && read32(&twi->reset))
udelay(1);
@@ -63,12 +63,12 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
static void clear_interrupt_flag(struct a1x_twi *twi)
{
- write32(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl);
+ writel(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl);
}
static void i2c_send_data(struct a1x_twi *twi, u8 data)
{
- write32(data, &twi->data);
+ writel(data, &twi->data);
clear_interrupt_flag(twi);
}
@@ -90,7 +90,7 @@ static void i2c_send_start(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_START;
- write32(reg32, &twi->ctl);
+ writel(reg32, &twi->ctl);
/* M_START is automatically cleared after condition is transmitted */
i = TWI_TIMEOUT;
@@ -106,7 +106,7 @@ static void i2c_send_stop(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_STOP;
- write32(reg32, &twi->ctl);
+ writel(reg32, &twi->ctl);
}
static int i2c_read(struct a1x_twi *twi, uint8_t chip,
diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c
index 407bd863aa..6883b4ea38 100644
--- a/src/cpu/allwinner/a10/uart.c
+++ b/src/cpu/allwinner/a10/uart.c
@@ -22,10 +22,10 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
div = (u16) uart_baudrate_divisor(baud_rate,
uart_platform_refclk(), 16);
/* Enable access to Divisor Latch register */
- write32(UART8250_LCR_DLAB, &uart->lcr);
+ writel(UART8250_LCR_DLAB, &uart->lcr);
/* Set baudrate */
- write32((div >> 8) & 0xff, &uart->dlh);
- write32(div & 0xff, &uart->dll);
+ writel((div >> 8) & 0xff, &uart->dlh);
+ writel(div & 0xff, &uart->dll);
/* Set line control */
reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK;
switch (parity) {
@@ -40,12 +40,12 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
default:
break;
}
- write32(reg32, &uart->lcr);
+ writel(reg32, &uart->lcr);
}
static void a10_uart_enable_fifos(struct a10_uart *uart)
{
- write32(UART8250_FCR_FIFO_EN, &uart->fcr);
+ writel(UART8250_FCR_FIFO_EN, &uart->fcr);
}
static int tx_fifo_full(struct a10_uart *uart)
@@ -83,7 +83,7 @@ static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data)
{
while (tx_fifo_full(uart)) ;
- return write32(data, &uart->thr);
+ return writel(data, &uart->thr);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 12:26:12 +0000