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-rw-r--r--src/config/failovercalculation.lb41
1 files changed, 0 insertions, 41 deletions
diff --git a/src/config/failovercalculation.lb b/src/config/failovercalculation.lb
deleted file mode 100644
index c0b35fe010..0000000000
--- a/src/config/failovercalculation.lb
+++ /dev/null
@@ -1,41 +0,0 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if CONFIG_USE_FAILOVER_IMAGE
- default CONFIG_ROM_SECTION_SIZE = CONFIG_FAILOVER_SIZE
- default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FAILOVER_SIZE )
- default CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
-else
- if CONFIG_USE_FALLBACK_IMAGE
- default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE
- default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
- else
- default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE
- default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
- end
-end
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## CONFIG_XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb
-## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
-##
-
-if CONFIG_USE_FAILOVER_IMAGE
- default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
-else
- if CONFIG_USE_FALLBACK_IMAGE
- default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE + CONFIG_FAILOVER_SIZE)
- else
- default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
- end
-end
-