diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/i386/boot/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/arch/i386/boot/mpspec.c (renamed from src/arch/i386/smp/mpspec.c) | 0 | ||||
| -rw-r--r-- | src/arch/i386/init/car.S | 363 | ||||
| -rw-r--r-- | src/arch/i386/lib/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/arch/i386/lib/ioapic.c (renamed from src/arch/i386/smp/ioapic.c) | 0 | ||||
| -rw-r--r-- | src/arch/i386/smp/Makefile.inc | 3 |
6 files changed, 2 insertions, 366 deletions
diff --git a/src/arch/i386/boot/Makefile.inc b/src/arch/i386/boot/Makefile.inc index 4ef5d6f386..0523341bd4 100644 --- a/src/arch/i386/boot/Makefile.inc +++ b/src/arch/i386/boot/Makefile.inc @@ -3,6 +3,7 @@ obj-y += coreboot_table.o obj-$(CONFIG_MULTIBOOT) += multiboot.o obj-y += gdt.o obj-y += tables.o +obj-$(CONFIG_GENERATE_MP_TABLE) += mpspec.o obj-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.o diff --git a/src/arch/i386/smp/mpspec.c b/src/arch/i386/boot/mpspec.c index 1beba873cc..1beba873cc 100644 --- a/src/arch/i386/smp/mpspec.c +++ b/src/arch/i386/boot/mpspec.c diff --git a/src/arch/i386/init/car.S b/src/arch/i386/init/car.S deleted file mode 100644 index 64743ef8fc..0000000000 --- a/src/arch/i386/init/car.S +++ /dev/null @@ -1,363 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> - * Copyright (C) 2005 Eswar Nallusamy, LANL - * Copyright (C) 2005 Tyan - * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan) - * Copyright (C) 2007 coresystems GmbH - * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH) - * Copyright (C) 2008 Carl-Daniel Hailfinger - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */ - -#include <arch/intel.h> - -#define ROM_CODE_SEG 0x08 -#define ROM_DATA_SEG 0x10 - -#define CACHE_RAM_CODE_SEG 0x18 -#define CACHE_RAM_DATA_SEG 0x20 - - /* When we come here we are in protected mode. We expand the stack - * and copy the data segment from ROM to the memory. - * - * After that, we call the chipset bootstrap routine that - * does what is left of the chipset initialization. - * - * NOTE: Aligned to 4 so that we are sure that the prefetch - * cache will be reloaded. - */ - .section .rom.text - .align 4 - .globl protected_stage0 -protected_stage0: - lgdt %cs:gdtptr - ljmp $ROM_CODE_SEG, $__protected_stage0 - -.globl __protected_stage0 -__protected_stage0: - /* Save the BIST result. */ - movl %eax, %ebp - - post_code(0x01) - - movw $ROM_DATA_SEG, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs - - /* Restore the BIST value to %eax. */ - movl %ebp, %eax - -.align 4 - -/* disable HyperThreading is done by eswar - * the other is very similar to the AMD CAR, except remove amd specific msr - */ - -#define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase CONFIG_DCACHE_RAM_BASE - -#include <cpu/x86/mtrr.h> - - /* Save the BIST result */ - movl %eax, %ebp - -CacheAsRam: - /* Check whether the processor has HT capability */ - movl $01, %eax - cpuid - btl $28, %edx - jnc NotHtProcessor - bswapl %ebx - cmpb $01, %bh - jbe NotHtProcessor - - /* It is a HT processor; Send SIPI to the other logical processor - * within this processor so that the CAR related common system - * registers are programmed accordingly - */ - - /* Use some register that is common to both logical processors - * as semaphore. Refer Appendix B, Vol.3 - */ - - xorl %eax, %eax - xorl %edx, %edx - movl $0x250, %ecx - wrmsr - - /* Figure out the logical AP's APIC ID; the following logic will work - * only for processors with 2 threads. - * - * Refer to Vol 3. Table 7-1 for details about this logic - */ - movl $0xFEE00020, %esi - movl (%esi), %ebx - andl $0xFF000000, %ebx - bswapl %ebx - btl $0, %ebx - jnc LogicalAP0 - andb $0xFE, %bl - jmp SendSIPI -LogicalAP0: - orb $0x01, %bl -SendSIPI: - bswapl %ebx /* ebx - logical AP's APIC ID */ - - /* Fill up the IPI command registers in the Local APIC mapped to - * default address and issue SIPI to the other logical processor - * within this processor die. - */ - -RetrySIPI: - movl %ebx, %eax - movl $0xFEE00310, %esi - movl %eax, (%esi) - - /* SIPI vector - F900:0000 */ - movl $0x000006F9, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - movl $0x30, %ecx -SIPIDelay: - pause - decl %ecx - jnz SIPIDelay - - movl (%esi), %eax - andl $0x00001000, %eax - jnz RetrySIPI - - /* Wait for the Logical AP to complete initialization */ -LogicalAPSIPINotdone: - movl $0x250, %ecx - rdmsr - orl %eax, %eax - jz LogicalAPSIPINotdone - - - -NotHtProcessor: - /* Set the default memory type and enable fixed and variable MTRRs */ - movl $MTRRdefType_MSR, %ecx - xorl %edx, %edx - /* Enable Variable and Fixed MTRRs */ - movl $0x00000c00, %eax - wrmsr - - /* Clear all MTRRs */ - xorl %edx, %edx - movl $fixed_mtrr_msr, %esi - -clear_fixed_var_mtrr: - lodsl (%esi), %eax - testl %eax, %eax - jz clear_fixed_var_mtrr_out - - movl %eax, %ecx - xorl %eax, %eax - wrmsr - - jmp clear_fixed_var_mtrr -clear_fixed_var_mtrr_out: - -/* 0x06 is the WB IO type for a given 4k segment. - * segs is the number of 4k segments in the area of the particular - * register we want to use for CAR. - * reg is the register where the IO type should be stored. - */ -.macro extractmask segs, reg -.if \segs <= 0 - /* The xorl here is superfluous because at the point of first execution - * of this macro, %eax and %edx are cleared. Later invocations of this - * macro will have a monotonically increasing segs parameter. - */ - xorl \reg, \reg -.elseif \segs == 1 - movl $0x06000000, \reg /* WB IO type */ -.elseif \segs == 2 - movl $0x06060000, \reg /* WB IO type */ -.elseif \segs == 3 - movl $0x06060600, \reg /* WB IO type */ -.elseif \segs >= 4 - movl $0x06060606, \reg /* WB IO type */ -.endif -.endm - -/* size is the cache size in bytes we want to use for CAR. - * windowoffset is the 32k-aligned window into CAR size - */ -.macro simplemask carsize, windowoffset -/* DO NOT CHANGE THE FORMATTING of the two lines below! Whitespace is - * interpreted as an argument delimiter by some versions of GNU as. */ - extractmask (((\carsize-\windowoffset)/0x1000)-4), %eax - extractmask (((\carsize-\windowoffset)/0x1000)), %edx -.endm - -#if CacheSize > 0x10000 -#error Invalid CAR size, must be at most 64k. -#endif -#if CacheSize < 0x1000 -#error Invalid CAR size, must be at least 4k. This is a processor limitation. -#endif -#if (CacheSize & (0x1000 - 1)) -#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. -#endif - -#if CacheSize > 0x8000 - /* enable caching for 32K-64K using fixed mtrr */ - movl $0x268, %ecx /* fix4k_c0000*/ - simplemask CacheSize, 0x8000 - wrmsr -#endif - - /* enable caching for 0-32K using fixed mtrr */ - movl $0x269, %ecx /* fix4k_c8000*/ - simplemask CacheSize, 0 - wrmsr - -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) -#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif - /* enable write base caching so we can do execute in place - * on the flash rom. - */ - movl $0x202, %ecx - xorl %edx, %edx - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $0x203, %ecx - movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax - wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff,%eax - movl %eax, %cr0 - - /* Read the range with lodsl*/ - movl $CacheBase, %esi - cld - movl $(CacheSize>>2), %ecx - rep lodsl - - /* Clear the range */ - movl $CacheBase, %edi - movl $(CacheSize>>2), %ecx - xorl %eax, %eax - rep stosl - - - /* TODO: make this a config variable */ -#if CARTEST - /* check the cache as ram */ - movl $CacheBase, %esi - movl $(CacheSize>>2), %ecx -.xin1: - movl %esi, %eax - movl %eax, (%esi) - decl %ecx - je .xout1 - add $4, %esi - jmp .xin1 -.xout1: - - movl $CacheBase, %esi -// movl $(CacheSize>>2), %ecx - movl $4, %ecx -.xin1x: - movl %esi, %eax - - movl $0x4000, %edx - movb %ah, %al -.testx1: - outb %al, $0x80 - decl %edx - jnz .testx1 - - movl (%esi), %eax - cmpb 0xff, %al - je .xin2 /* dont show */ - - movl $0x4000, %edx -.testx2: - outb %al, $0x80 - decl %edx - jnz .testx2 - -.xin2: decl %ecx - je .xout1x - add $4, %esi - jmp .xin1x -.xout1x: - -#endif - - movl $(CacheBase+CacheSize-4), %eax - movl %eax, %esp - - /* Load a different set of data segments */ - movw $CACHE_RAM_DATA_SEG, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - -lout: - /* Store zero for the pointer to the global variables. */ - pushl $0 - - /* Restore the BIST result. */ - movl %ebp, %eax - - /* We need to set ebp? No need. */ - movl %esp, %ebp - - /* Third parameter: cpu #: 0 == BSP all other are APs. - * 0 until SMP support is added. - */ - pushl $0 - /* Second parameter: init_detected */ - /* Store zero for the unused init_detected parameter. */ - pushl $0 - /* First parameter: bist */ - pushl %eax - call main - /* We will not go back. */ - -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ diff --git a/src/arch/i386/lib/Makefile.inc b/src/arch/i386/lib/Makefile.inc index 41f8fdc581..de61f9e42c 100644 --- a/src/arch/i386/lib/Makefile.inc +++ b/src/arch/i386/lib/Makefile.inc @@ -5,6 +5,7 @@ obj-y += pci_ops_conf2.o obj-y += pci_ops_mmconf.o obj-y += pci_ops_auto.o obj-y += exception.o +obj-$(CONFIG_IOAPIC) += ioapic.o initobj-y += printk_init.o initobj-y += cbfs_and_run.o diff --git a/src/arch/i386/smp/ioapic.c b/src/arch/i386/lib/ioapic.c index efc2ac52fc..efc2ac52fc 100644 --- a/src/arch/i386/smp/ioapic.c +++ b/src/arch/i386/lib/ioapic.c diff --git a/src/arch/i386/smp/Makefile.inc b/src/arch/i386/smp/Makefile.inc deleted file mode 100644 index 44190587b9..0000000000 --- a/src/arch/i386/smp/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -obj-$(CONFIG_GENERATE_MP_TABLE) += mpspec.o -obj-$(CONFIG_IOAPIC) += ioapic.o - |