diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/Kconfig | 16 | ||||
| -rw-r--r-- | src/arch/x86/car.ld | 20 |
2 files changed, 36 insertions, 0 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index f5bbd7827e..d7f144e179 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -286,3 +286,19 @@ config COLLECT_TIMESTAMPS_TSC depends on COLLECT_TIMESTAMPS help Use the TSC as the timestamp source. + +config PAGING_IN_CACHE_AS_RAM + bool + default n + depends on ARCH_X86 + help + Chipsets scan select this option to preallocate area in cache-as-ram + for storing paging data structures. PAE paging is currently the + only thing being supported. + +config NUM_CAR_PAGE_TABLE_PAGES + int + default 5 + depends on PAGING_IN_CACHE_AS_RAM + help + The number of 4KiB pages that should be pre-allocated for page tables. diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index bfc1b03bd3..2acd3f673f 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -19,6 +19,13 @@ . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { _car_region_start = . ; +#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) + /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB + * aligned when using this option. */ + _pagetables = . ; + . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; + _epagetables = . ; +#endif /* Vboot work buffer is completely volatile outside of verstage and * romstage. Appropriate code needs to handle the transition. */ #if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE) @@ -37,6 +44,16 @@ * so that multiple stages (romstage and verstage) have a consistent * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)) +#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) + . = ALIGN(32); + /* Page directory pointer table resides here. There are 4 8-byte entries + * totalling 32 bytes that need to be 32-byte aligned. The reason the + * pdpt are not colocated with the rest of the page tables is to reduce + * fragmentation of the CAR space that persists across stages. */ + _pdpt = .; + . += 32; + _epdpt = .; +#endif _car_relocatable_data_start = .; /* The timestamp implementation relies on this storage to be around * after migration. One of the fields indicates not to use it as the @@ -78,3 +95,6 @@ } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); +#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) +_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); +#endif |