diff options
Diffstat (limited to 'src/arch')
35 files changed, 220 insertions, 1248 deletions
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index cd6c4a4e21..4b8b473cb7 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -63,11 +63,9 @@ bootblock-y += memmove.S bootblock-y += div0.c bootblock-y += clock.c -bootblock-y += bootblock.ld - -$(objcbfs)/bootblock.debug: $(obj)/arch/arm/bootblock.bootblock.ld $$(bootblock-objs) $$(VERSTAGE_LIB) +$(objcbfs)/bootblock.debug: $$(bootblock-objs) $$(VERSTAGE_LIB) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/arm/bootblock.bootblock.ld --start-group $(bootblock-objs) --end-group + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -75,9 +73,9 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM # verification stage ############################################################################### -$(objcbfs)/verstage.debug: $$(verstage-objs) $(obj)/arch/arm/verstage.verstage.ld $$(VB2_LIB) +$(objcbfs)/verstage.debug: $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $$(VB2_LIB) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/arm/verstage.verstage.ld --start-group $(verstage-objs) --end-group + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(verstage-objs) --end-group verstage-y += div0.c verstage-y += eabi_compat.c @@ -86,8 +84,6 @@ verstage-y += memcpy.S verstage-y += memmove.S verstage-y += stages.c -verstage-y += verstage.ld - ############################################################################### # romstage ############################################################################### @@ -107,13 +103,11 @@ rmodules_arm-y += memcpy.S rmodules_arm-y += memmove.S rmodules_arm-y += eabi_compat.c -romstage-y += romstage.ld - VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o -$(objcbfs)/romstage.debug: $$(romstage-objs) $(obj)/arch/arm/romstage.romstage.ld +$(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/arm/romstage.romstage.ld --start-group $(romstage-objs) --end-group + $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_ARM @@ -133,20 +127,15 @@ ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S ramstage-y += clock.c + rmodules_arm-y += memset.S rmodules_arm-y += memcpy.S rmodules_arm-y += memmove.S rmodules_arm-y += eabi_compat.c ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) -ramstage-y += ramstage.ld - -$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(obj)/arch/arm/ramstage.ramstage.ld - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/arch/arm/ramstage.ramstage.ld --start-group $(ramstage-objs) --end-group - -$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) +$(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -r -o $@ --start-group $(ramstage-objs) --end-group + $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S index e4d43029fe..1a30dda65e 100644 --- a/src/arch/arm/armv4/bootblock.S +++ b/src/arch/arm/armv4/bootblock.S @@ -44,10 +44,8 @@ ENTRY(_start) * Initialize the stack to a known value. This is used to check for * stack overflow later in the boot process. */ - ldr r0, .Stack - ldr r1, .Stack_size - sub r0, r0, r1 - ldr r1, .Stack + ldr r0, =_stack + ldr r1, =_estack ldr r2, =0xdeadbeef init_stack_loop: str r2, [r0] @@ -57,7 +55,7 @@ init_stack_loop: /* Set stackpointer in internal RAM to call bootblock main() */ call_bootblock: - ldr sp, .Stack /* Set up stack pointer */ + ldr sp, =_estack /* Set up stack pointer */ ldr r0,=0x00000000 /* * The current design of cpu_info places the @@ -75,15 +73,3 @@ call_bootblock: */ bl main ENDPROC(_start) - -/* we do it this way because it's a 32-bit constant and - * in some cases too far away to be loaded as just an offset - * from IP - */ -.align 2 -.Stack: - .word CONFIG_STACK_TOP -.align 2 -/* create this size the same way we do in coreboot_ram.ld: top-bottom */ -.Stack_size: - .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index a15d1672ca..b468e15c98 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -62,10 +62,8 @@ ENTRY(_thumb_start) * Initialize the stack to a known value. This is used to check for * stack overflow later in the boot process. */ - ldr r0, .Stack - ldr r1, .Stack_size - sub r0, r0, r1 - ldr r1, .Stack + ldr r0, =_stack + ldr r1, =_estack ldr r2, =0xdeadbeef init_stack_loop: str r2, [r0] @@ -75,7 +73,7 @@ init_stack_loop: /* Set stackpointer in internal RAM to call bootblock main() */ call_bootblock: - ldr sp, .Stack /* Set up stack pointer */ + ldr sp, =_estack /* Set up stack pointer */ ldr r0,=0x00000000 /* * The current design of cpu_info places the struct at the top of the @@ -89,15 +87,3 @@ wait_for_interrupt: wfi mov pc, lr @ back to my caller ENDPROC(_thumb_start) - -/* we do it this way because it's a 32-bit constant and - * in some cases too far away to be loaded as just an offset - * from IP - */ -.align 2 -.Stack: - .word CONFIG_STACK_TOP -.align 2 -/* create this size the same way we do in coreboot_ram.ld: top-bottom */ -.Stack_size: - .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index bd12946d2e..e9c681530c 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -31,6 +31,7 @@ #include <config.h> #include <stdlib.h> #include <stdint.h> +#include <symbols.h> #include <cbmem.h> #include <console/console.h> @@ -90,7 +91,7 @@ typedef uint32_t pmd_t; static const unsigned int denom = 1; #endif /* CONFIG_ARM_LPAE */ -static pmd_t *const ttb_buff = (pmd_t *)CONFIG_TTB_BUFFER; +static pmd_t *const ttb_buff = (pmd_t *)_ttb; /* * mask/shift/size for pages and blocks @@ -186,7 +187,7 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, void mmu_init(void) { if (CONFIG_ARM_LPAE) { - pgd_t *const pgd_buff = (pgd_t*)(CONFIG_TTB_BUFFER + 16*KiB); + pgd_t *const pgd_buff = (pgd_t*)(_ttb + 16*KiB); pmd_t *pmd = ttb_buff; int i; diff --git a/src/arch/arm/bootblock.ld b/src/arch/arm/include/arch/header.ld index 091e3ebdd6..2138c774be 100644 --- a/src/arch/arm/bootblock.ld +++ b/src/arch/arm/include/arch/header.ld @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,34 +26,8 @@ PHDRS to_load PT_LOAD; } +#ifdef __BOOTBLOCK__ ENTRY(_start) -SECTIONS -{ - . = CONFIG_BOOTBLOCK_BASE; - - .bootblock . : { - *(.text._start); - KEEP(*(.id)); - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - *(.bss); - *(.bss.*); - *(.sbss); - *(.sbss.*); - _end = .; - } : to_load = 0xff - - preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.ARM.*) - } -} +#else +ENTRY(stage_entry) +#endif diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h new file mode 100644 index 0000000000..9f5b383160 --- /dev/null +++ b/src/arch/arm/include/arch/memlayout.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file contains macro definitions for memlayout.ld linker scripts. */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +#define TTB(addr, size) \ + REGION(ttb, addr, size, 16K) \ + _ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \ + "TTB must be 16K (+ 32 for LPAE)!"); + +/* ARM stacks need 8-byte alignment and stay in one place through ramstage. */ +#define STACK(addr, size) REGION(stack, addr, size, 8) + +#define DMA_COHERENT(addr, size) \ + REGION(dma_coherent, addr, size, (1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) \ + _ = ASSERT(size % ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) == 0, \ + "DMA coherency buffer must fit exactly in full superpages!"); + +#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/arm/include/arch/stages.h b/src/arch/arm/include/arch/stages.h index 39fed990c5..1a0dcc1f86 100644 --- a/src/arch/arm/include/arch/stages.h +++ b/src/arch/arm/include/arch/stages.h @@ -22,7 +22,7 @@ extern void main(void); -void stage_entry(void) __attribute__((section(".text.stage_entry.arm"))); +void stage_entry(void); void stage_exit(void *); #endif diff --git a/src/arch/arm/ramstage.ld b/src/arch/arm/ramstage.ld deleted file mode 100644 index 7daa8cbbb8..0000000000 --- a/src/arch/arm/ramstage.ld +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Memory map: - * - * CONFIG_RAMSTAGE_BASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add ramstage cross the vga font buffer handling - */ - -ENTRY(stage_entry) - -PHDRS -{ - to_load PT_LOAD; -} - -SECTIONS -{ - . = CONFIG_RAMSTAGE_BASE; - /* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ - .text : { - _text = .; - _start = .; - *(.text.stage_entry.arm); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } : to_load - - .ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - KEEP(*(.ctors)); - LONG(0); - __CTOR_END__ = .; - } - - .rodata : { - _rodata = .; - . = ALIGN(4); - pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - epci_drivers = . ; - cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - _bs_init_end = .; - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(4); - - _erodata = .; - } - /* After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - *(.data.*) - _edata = .; - } - - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - .bss . : { - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - } - _end = .; - - /* coreboot really "ends" here. Only heap and stack are placed after - * this line. - */ - - .heap . : { - _heap = .; - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - _eheap = .; - } - - /* The ram segment. This includes all memory used by the memory - * resident copy of coreboot, except the tables that are produced on - * the fly, but including stack and heap. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - /* The stack lives in SRAM in a different location, so keep - * it out of ram_seg - */ - _stack = CONFIG_STACK_BOTTOM; - _estack = CONFIG_STACK_TOP; - - /* Discard the sections we don't need/want */ - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} diff --git a/src/arch/arm/romstage.ld b/src/arch/arm/romstage.ld deleted file mode 100644 index d107687c90..0000000000 --- a/src/arch/arm/romstage.ld +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Memory map: - * - * CONFIG_ROMSTAGE_BASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add ramstage cross the vga font buffer handling - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) - -ENTRY(stage_entry) - -PHDRS -{ - to_load PT_LOAD; -} - -SECTIONS -{ - . = CONFIG_ROMSTAGE_BASE; - - .romtext . : { - _start = .; - *(.text.stage_entry.arm); - *(.text.startup); - *(.text); - *(.text.*); - } : to_load - - .romdata . : { - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - . = ALIGN(8); - } - - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - .bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - } - - _end = .; - - preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; - - /* Discard the sections we don't need/want */ - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } -} diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index 47f13fa71d..11acc9bd7b 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -22,10 +22,10 @@ * execution (bootblock entry and ramstage exit will depend on external * loading). * - * Entry points must be placed at the location the previous stage jumps - * to (the lowest address in the stage image). This is done by giving - * stage_entry() its own section in .text and placing it first in the - * linker script. + * Entry points should be set in the linker script and honored by CBFS, + * so text section layout shouldn't matter. Still, it doesn't hurt to put + * stage_entry first (which XXXstage.ld will do automatically through the + * .text.stage_entry section created by -ffunction-sections). */ #include <arch/stages.h> diff --git a/src/arch/arm/verstage.ld b/src/arch/arm/verstage.ld deleted file mode 100644 index 88d4bc8dfb..0000000000 --- a/src/arch/arm/verstage.ld +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Memory map: - * - * CONFIG_VERSTAGE_BASE : text segment - * : rodata segment - * : data segment - * : bss segment - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) - -PHDRS -{ - to_load PT_LOAD; -} - -ENTRY(stage_entry) - -SECTIONS -{ - . = CONFIG_VERSTAGE_BASE; - - .romtext . : { - _start = .; - *(.text.stage_entry.arm); - *(.text.startup); - *(.text); - *(.text.*); - } : to_load - - .romdata . : { - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - . = ALIGN(8); - } - - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - */ - .bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - } - - _end = .; - - preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; - - /* Discard the sections we don't need/want */ - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } -} diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index a9fbde5acd..b2b627c07f 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -68,13 +68,11 @@ bootblock-y += ../../lib/memset.c bootblock-y += ../../lib/memcpy.c bootblock-y += ../../lib/memmove.c -bootblock-y += bootblock.ld - # Build the bootblock -$(objcbfs)/bootblock.debug: $(obj)/arch/arm64/bootblock.bootblock.ld $$(bootblock-objs) $(obj)/config.h +$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(obj)/arch/arm64/bootblock.bootblock.ld + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -96,8 +94,6 @@ romstage-y += ../../lib/memmove.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-y += transition.c transition_asm.S -romstage-y += romstage.ld - rmodules_arm64-y += ../../lib/memset.c rmodules_arm64-y += ../../lib/memcpy.c rmodules_arm64-y += ../../lib/memmove.c @@ -106,9 +102,9 @@ rmodules_arm64-y += eabi_compat.c # Build the romstage VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o -$(objcbfs)/romstage.debug: $$(romstage-objs) $(obj)/arch/arm64/romstage.romstage.ld +$(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(romstage-objs) --end-group -T $(obj)/arch/arm64/romstage.romstage.ld + $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld endif # CONFIG_ARCH_ROMSTAGE_ARM64 @@ -144,18 +140,13 @@ secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcmp.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcpy.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -ramstage-y += ramstage.ld ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) # Build the ramstage -$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(obj)/arch/arm64/ramstage.ramstage.ld - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --start-group $(ramstage-objs) --end-group -T $(obj)/arch/arm64/ramstage.ramstage.ld - -$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) +$(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -r -o $@ --start-group $(ramstage-objs) --end-group + $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/bootblock.ld b/src/arch/arm64/include/arch/header.ld index 98c6454182..bb32a93554 100644 --- a/src/arch/arm64/bootblock.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,38 +26,7 @@ PHDRS to_load PT_LOAD; } -ENTRY(stage_entry) +#ifdef __BOOTBLOCK__ TARGET(binary) -SECTIONS -{ - . = CONFIG_BOOTBLOCK_BASE; - - .bootblock . : { - *(.text.stage_entry); - KEEP(*(.id)); - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - *(.bss); - *(.bss.*); - *(.sbss); - *(.sbss.*); - } : to_load = 0xff - - /* arm64 chipsets need to define CONFIG_BOOTBLOCK_STACK_(TOP|BOTTOM) */ - _stack = CONFIG_BOOTBLOCK_STACK_BOTTOM; - _estack = CONFIG_BOOTBLOCK_STACK_TOP; - - preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.ARM.*) - } -} +#endif +ENTRY(stage_entry) diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h new file mode 100644 index 0000000000..328156bf3a --- /dev/null +++ b/src/arch/arm64/include/arch/memlayout.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file contains macro definitions for memlayout.ld linker scripts. */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +/* TODO: add SRAM TTB region and figure out the correct size/alignment for it */ + +/* ARM64 stacks need 16-byte alignment. The ramstage will set up its own stacks + * in BSS, so this is only used for the SRAM stages. */ +#ifdef __PRE_RAM__ +#define STACK(addr, size) REGION(stack, addr, size, 16) +#else +#define STACK(addr, size) REGION(preram_stack, addr, size, 16) +#endif + +#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld deleted file mode 100644 index 7022e4f151..0000000000 --- a/src/arch/arm64/ramstage.ld +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Memory map: - * - * CONFIG_RAMBASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -/* - * Copyright 2013 Google Inc. - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add ramstage cross the vga font buffer handling - */ - -ENTRY(stage_entry) - -PHDRS -{ - to_load PT_LOAD; -} - -SECTIONS -{ - . = CONFIG_RAMSTAGE_BASE; - - .text : { - _text = .; - _start = .; - *(.text.stage_entry); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } : to_load - - .ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - KEEP(*(.ctors)); - LONG(0); - LONG(0); - __CTOR_END__ = .; - } - - .rodata : { - . = ALIGN(64); - _rodata = .; - console_drivers = .; - KEEP(*(.rodata.console_drivers)); - econsole_drivers = . ; - . = ALIGN(64); - pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - epci_drivers = . ; - cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - . = ALIGN(64); - *(.rodata) - *(.rodata.*) - _erodata = .; - } - - .data : { - . = ALIGN(64); - _data = .; - *(.data) - *(.data.*) - . = ALIGN(64); - _edata = .; - } - - .bss : { - . = ALIGN(64); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss.*) - *(COMMON) - . = ALIGN(64); - _ebss = .; - } - - .heap : { - _heap = .; - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = . + CONFIG_HEAP_SIZE ; - . = ALIGN(64); - _eheap = .; - } - - /* The ram segment. This includes all memory used by the memory - * resident copy of coreboot, except the tables that are produced on - * the fly, but including stack and heap. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - /* Discard the sections we don't need/want */ - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} diff --git a/src/arch/arm64/romstage.ld b/src/arch/arm64/romstage.ld deleted file mode 100644 index fef2ac50fc..0000000000 --- a/src/arch/arm64/romstage.ld +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Memory map: - * - * CONFIG_ROMSTAGE_BASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add ramstage cross the vga font buffer handling - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") -OUTPUT_ARCH(aarch64) - -PHDRS -{ - to_load PT_LOAD; -} - -ENTRY(stage_entry) - -SECTIONS -{ - . = CONFIG_ROMSTAGE_BASE; - - .romtext . : { - _start = .; - *(.text.stage_entry); - *(.text.startup); - *(.text); - *(.text.*); - } : to_load - - .romdata . : { - *(.rodata); - *(.rodata.*); - *(.machine_param); - *(.data); - *(.data.*); - . = ALIGN(8); - _erom = .; - } - - __image_copy_end = .; - - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - .bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - } - - _end = .; - - /* arm64 chipsets need to define CONFIG_ROMSTAGE_STACK_(TOP|BOTTOM) */ - _stack = CONFIG_ROMSTAGE_STACK_BOTTOM; - _estack = CONFIG_ROMSTAGE_STACK_TOP; - - preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; - - /* Discard the sections we don't need/want */ - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } -} diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index 969a03d2e3..9e88ba8ce8 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -43,17 +43,15 @@ bootblock-y += ../../lib/memcpy.c bootblock-y += ../../lib/memmove.c bootblock-y += ../../lib/memset.c -bootblock-y += bootblock.ld - # Much of the assembly code is generated by the compiler, and may contain # terms which the preprocessor will happily go on to replace. For example # "mips" would be replaced with "1". Clear all the built in definitions to # prevent that. bootblock-S-ccopts += -undef -$(objcbfs)/bootblock.debug: $(obj)/arch/mips/bootblock.bootblock.ld $$(bootblock-objs) $(obj)/config.h +$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/mips/bootblock.bootblock.ld --start-group $(bootblock-objs) --end-group + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_MIPS @@ -71,11 +69,9 @@ romstage-y += ../../lib/memcpy.c romstage-y += ../../lib/memmove.c romstage-y += ../../lib/memset.c -romstage-y += romstage.ld - -$(objcbfs)/romstage.debug: $$(romstage-objs) $(obj)/arch/mips/romstage.romstage.ld +$(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/mips/romstage.romstage.ld --start-group $(romstage-objs) --end-group + $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_MIPS @@ -93,12 +89,11 @@ ramstage-y += timer.c ramstage-y += ../../lib/memcpy.c ramstage-y += ../../lib/memmove.c ramstage-y += ../../lib/memset.c -ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) -ramstage-y += ramstage.ld +ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) -$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(obj)/arch/mips/ramstage.ramstage.ld +$(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/mips/ramstage.ramstage.ld --start-group $(ramstage-objs) --end-group + $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_MIPS diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S index f369e006fa..8899fe0a97 100644 --- a/src/arch/mips/bootblock.S +++ b/src/arch/mips/bootblock.S @@ -19,17 +19,17 @@ .set noreorder /* Prevent assembler from "optimizing" this code. */ -.section ".start", "ax", %progbits +.section ".text._start", "ax", %progbits .globl _start _start: /* Set the stack pointer */ - li $sp, CONFIG_BOOTBLOCK_STACK_TOP + la $sp, _estack /* * Initialise the stack to a known value, used later to check for * overflow. */ - li $t0, CONFIG_BOOTBLOCK_STACK_BOTTOM + la $t0, _stack addi $t1, $sp, -4 li $t2, 0xdeadbeef 1: sw $t2, 0($t0) diff --git a/src/arch/mips/bootblock.ld b/src/arch/mips/include/arch/header.ld index 3721f85641..0c7d7a1582 100644 --- a/src/arch/mips/bootblock.ld +++ b/src/arch/mips/include/arch/header.ld @@ -1,9 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * Copyright (C) 2014 Imagination Technologies + * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,39 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_ARCH(mips) -ENTRY(_start) - PHDRS { to_load PT_LOAD; } -preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; - -SECTIONS -{ - . = CONFIG_BOOTBLOCK_BASE; - - /* This section might be better named .setup */ - .rom : { - _rom = .; - *(.start); - *(.id); - *(.text); - *(.text.*); - *(.rom.text); - *(.rom.data); - *(.rom.data.*); - *(.rodata.*); - _erom = .; - } : to_load = 0xff - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - } -} +#ifdef __BOOTBLOCK__ +ENTRY(_start) +#else +ENTRY(stage_entry) +#endif diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h new file mode 100644 index 0000000000..4cbbe1d02b --- /dev/null +++ b/src/arch/mips/include/arch/memlayout.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file contains macro definitions for memlayout.ld linker scripts. */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +/* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */ +/* TODO: Double-check that that's the correct alignment for our ABI. */ +#define STACK(addr, size) REGION(stack, addr, size, 8) + +/* TODO: Need to add DMA_COHERENT region like on ARM? */ + +#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/mips/ramstage.ld b/src/arch/mips/ramstage.ld deleted file mode 100644 index 405244446f..0000000000 --- a/src/arch/mips/ramstage.ld +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * Based on src/arch/arm/ramstage.ld: - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -OUTPUT_ARCH(mips) - -ENTRY(stage_entry) - -PHDRS -{ - to_load PT_LOAD; -} - -SECTIONS -{ - . = CONFIG_SYS_SDRAM_BASE; - - .text : { - _text = .; - _start = .; - *(.text.stage_entry.mips); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } : to_load - - .ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - *(.ctors); - LONG(0); - __CTOR_END__ = .; - } - - .rodata : { - _rodata = .; - . = ALIGN(4); - console_drivers = .; - KEEP(*(.rodata.console_drivers)); - econsole_drivers = . ; - . = ALIGN(4); - pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - epci_drivers = . ; - cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - _bs_init_end = .; - *(.rodata) - *(.rodata.*) - . = ALIGN(4); - _erodata = .; - } - - .data : { - _data = .; - *(.data) - _edata = .; - } - - /* bss will be cleared by cbfs_load_stage */ - _bss = .; - .bss . : { - *(.bss) - *(.sbss) - *(COMMON) - } - _ebss = .; - _end = .; - - /* - * coreboot from the perspective of the loader really "ends" - * here. Only symbols are placed after this. - */ - - _heap = .; - _eheap = . + CONFIG_HEAP_SIZE; - - _stack = CONFIG_STACK_BOTTOM; - _estack = CONFIG_STACK_TOP; - - /* - * The ram segment. This includes all memory used by the memory - * resident copy of coreboot, except the tables that are produced on - * the fly, but including stack and heap. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - /* Discard the sections we don't need/want */ - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} diff --git a/src/arch/mips/romstage.ld b/src/arch/mips/romstage.ld deleted file mode 100644 index 8964285230..0000000000 --- a/src/arch/mips/romstage.ld +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -OUTPUT_ARCH(mips) - -ENTRY(stage_entry) - -PHDRS -{ - to_load PT_LOAD; -} - -preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; - -SECTIONS -{ - . = CONFIG_ROMSTAGE_BASE; - - .romtext . : { - _rom = .; - _start = .; - *(.text.stage_entry.mips); - *(.text.startup); - *(.text); - } : to_load - - .romdata . : { - *(.rodata); - *(.data); - . = ALIGN(16); - _erom = .; - } - - /* bss will be cleared by cbfs_load_stage */ - .bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.sbss) - *(COMMON) - } - - _ebss = .; - _end = .; - - /* Discard the sections we don't need/want */ - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } -} diff --git a/src/arch/mips/stages.c b/src/arch/mips/stages.c index ae10594288..79b2ea4cd8 100644 --- a/src/arch/mips/stages.c +++ b/src/arch/mips/stages.c @@ -20,7 +20,7 @@ #include <arch/stages.h> #include <arch/cache.h> - __attribute__((section(".text.stage_entry.mips"))) void stage_entry(void) +void stage_entry(void) { main(); } diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 643facff8e..7f55e1fa3e 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -38,12 +38,10 @@ bootblock-y += \ $(top)/src/lib/memmove.c \ $(top)/src/lib/memset.c -bootblock-y += bootblock.ld - -$(objcbfs)/bootblock.debug: $(obj)/arch/riscv/bootblock.bootblock.ld $$(bootblock-objs) +$(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \ - -T $(obj)/arch/riscv/bootblock.bootblock.ld --start-group $(bootblock-objs) \ + -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) \ $(LIBGCC_FILE_NAME_bootblock) --end-group endif @@ -65,13 +63,11 @@ romstage-y += \ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -romstage-y += romstage.ld - # Build the romstage -$(objcbfs)/romstage.debug: $$(romstage-objs) $(obj)/arch/riscv/romstage.romstage.ld +$(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/riscv/romstage.romstage.ld --start-group $(romstage-objs) --end-group + $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) @@ -103,15 +99,13 @@ $(eval $(call create_class_compiler,rmodules,riscv)) ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -ramstage-y += ramstage.ld - ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c # Build the ramstage -$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(obj)/arch/riscv/ramstage.ramstage.ld +$(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/riscv/ramstage.ramstage.ld --start-group $(ramstage-objs) --end-group + $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 00962c4c19..1461a9cbc5 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -21,7 +21,7 @@ // See LICENSE for license details. relating to the _start code in this file. #include <arch/encoding.h> -.section ".start", "ax", %progbits +.section ".text._start", "ax", %progbits // Maybe there's a better way. .space 0x2000 .globl _start diff --git a/src/arch/riscv/bootblock.ld b/src/arch/riscv/include/arch/header.ld index e5cb851b39..3c42099905 100644 --- a/src/arch/riscv/bootblock.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,7 +18,6 @@ */ /* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") OUTPUT_ARCH(riscv) PHDRS @@ -27,30 +25,9 @@ PHDRS to_load PT_LOAD; } +#ifdef __BOOTBLOCK__ ENTRY(_start) -SECTIONS -{ - . = CONFIG_BOOTBLOCK_BASE; - - .bootblock . : { - *(.start); - KEEP(*(.id)); - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - *(.bss); - *(.bss.*); - *(.sbss); - *(.sbss.*); - } : to_load = 0xff +#else +ENTRY(stage_entry) +#endif - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - } -} diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h new file mode 100644 index 0000000000..b6f4cba214 --- /dev/null +++ b/src/arch/riscv/include/arch/memlayout.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file contains macro definitions for memlayout.ld linker scripts. */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +/* TODO: Double-check that that's the correct alignment for our ABI. */ +#define STACK(addr, size) REGION(stack, addr, size, 8) + +/* TODO: Need to add DMA_COHERENT region like on ARM? */ + +#endif /* __ARCH_MEMLAYOUT_H */ + diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h index 2d1192ae35..3b8543da7f 100644 --- a/src/arch/riscv/include/arch/stages.h +++ b/src/arch/riscv/include/arch/stages.h @@ -22,7 +22,7 @@ extern void main(void); -void stage_entry(void) __attribute__((section(".text.stage_entry.riscv"))); +void stage_entry(void) __attribute__((section(".text.stage_entry"))); void stage_exit(void *); void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); diff --git a/src/arch/riscv/ramstage.ld b/src/arch/riscv/ramstage.ld deleted file mode 100644 index 21c9638792..0000000000 --- a/src/arch/riscv/ramstage.ld +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Memory map: - * - * CONFIG_RAMBASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -/* - * Copyright 2013 Google Inc. - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add ramstage cross the vga font buffer handling - */ - -ENTRY(stage_entry) - -PHDRS -{ - to_load PT_LOAD; -} - -SECTIONS -{ - . = 0x100000; /*CONFIG_SYS_SDRAM_BASE;*/ - /* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ - .text : { - _text = .; - _start = .; - *(.text.stage_entry.riscv); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } : to_load - - .ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - *(.ctors); - LONG(0); - __CTOR_END__ = .; - } - - .rodata : { - _rodata = .; - . = ALIGN(4); - console_drivers = .; - *(.rodata.console_drivers) - econsole_drivers = . ; - . = ALIGN(4); - pci_drivers = . ; - *(.rodata.pci_driver) - epci_drivers = . ; - cpu_drivers = . ; - *(.rodata.cpu_driver) - ecpu_drivers = . ; - _bs_init_begin = .; - *(.bs_init) - LONG(0); - _bs_init_end = .; - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(4); - - _erodata = .; - } - /* After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } - - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - _bss = .; - .bss . : { - *(.bss) - *(.sbss) - *(COMMON) - } - _ebss = .; - _end = .; - - /* coreboot really "ends" here. Only heap and stack are placed after - * this line. - */ - - _heap = .; - .heap . : { - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; - - _stack = CONFIG_STACK_BOTTOM; - _estack = CONFIG_STACK_TOP; - - /* The ram segment. This includes all memory used by the memory - * resident copy of coreboot, except the tables that are produced on - * the fly, but including stack and heap. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - /* Discard the sections we don't need/want */ - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} diff --git a/src/arch/riscv/romstage.ld b/src/arch/riscv/romstage.ld deleted file mode 100644 index e49d1c10aa..0000000000 --- a/src/arch/riscv/romstage.ld +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Memory map: - * - * CONFIG_ROMSTAGE_BASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add ramstage cross the vga font buffer handling - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") -OUTPUT_ARCH(riscv) - -PHDRS -{ - to_load PT_LOAD; -} - -ENTRY(stage_entry) - -SECTIONS -{ - . = CONFIG_ROMSTAGE_BASE; - - .romtext . : { - _start = .; - *(.text.stage_entry.riscv); - *(.text.startup); - *(.text); - *(.text.*); - } : to_load - - .romdata . : { - *(.rodata); - *(.rodata.*); - *(.machine_param); - *(.data); - *(.data.*); - . = ALIGN(8); - _erom = .; - } - - __image_copy_end = .; - - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - .bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - } - - _end = .; - - preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; - - /* Discard the sections we don't need/want */ - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } -} diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 065b7778fd..e48913cef5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -303,7 +303,7 @@ ramstage-srcs += $(src)/arch/x86/ramstage.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld + $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld endif diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 08fabcfb4f..0ff8a6c37f 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -3,6 +3,7 @@ #include <program_loading.h> #include <ip_checksum.h> #include <string.h> +#include <symbols.h> /* When the ramstage is relocatable the elf loading ensures an elf image cannot * be loaded over the ramstage code. */ @@ -25,11 +26,10 @@ static void jmp_payload_no_bounce_buffer(void *entry) static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) { - extern unsigned char _ram_seg, _eram_seg; unsigned long lb_start, lb_size; - lb_start = (unsigned long)&_ram_seg; - lb_size = (unsigned long)(&_eram_seg - &_ram_seg); + lb_start = (unsigned long)&_program; + lb_size = _program_size; printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry); printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start); diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 40ed3544a1..2ae96aca40 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -60,12 +60,12 @@ SECTIONS *(.car.global_data); _car_data_end = .; /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents that - * grows to a bound of CONFIG_CONSOLE_PRERAM_BUFFER_SIZE. + * of a zero-sized array to hold the memconsole contents. * However, collisions within the cache-as-ram region cannot be * statically checked because the cache-as-ram region usage is * cpu/chipset dependent. */ - preram_cbmem_console = .; + _preram_cbmem_console = .; + _epreram_cbmem_console = . + 0xc00; } /* Global variables are not allowed in romstage @@ -83,5 +83,5 @@ SECTIONS *(.sbss.*) } - _bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); + _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); } diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 675a09ce72..dbed12377e 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -16,7 +16,7 @@ thread_stacks: .space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS #endif - .section ".textfirst", "ax", @progbits + .section ".text._start", "ax", @progbits .code32 .globl _start .globl __rmodule_entry diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index f765cbe6f9..5fcbbb632a 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -8,121 +8,18 @@ * : stack * : heap */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add ramstage cross the vga font buffer handling - */ - ENTRY(_start) +PHDRS +{ + to_load PT_LOAD; +} + SECTIONS { . = CONFIG_RAMBASE; - /* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ - .text : { - _text = .; - *(.textfirst); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } - - .ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - KEEP(*(.ctors)); - LONG(0); - __CTOR_END__ = .; - } - - .rodata : { - _rodata = .; - . = ALIGN(4); - - /* If any changes are made to the driver start/symbols or the - * section names the equivalent changes need to made to - * rmodule.ld. */ - pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - epci_drivers = . ; - cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - _bs_init_end = .; - - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(4); - - _erodata = .; - } - /* After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - *(.data.*) - _edata = .; - } - - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - _bss = .; - .bss . : { - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - *(COMMON) - } - _ebss = .; - - _heap = .; - .heap . : { - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; - - /* The ram segment. This includes all memory used by the memory - * resident copy of coreboot, except the tables that are produced on - * the fly, but including stack and heap. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - /* CONFIG_RAMTOP is the upper address of cached memory (among other - * things). We must not exceed beyond that address, there be dragons. - */ - _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); - /* Discard the sections we don't need/want */ + INCLUDE "lib/ramstage.ramstage.ld" - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } + _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); } |