diff options
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/assembly_entry.S | 44 |
1 files changed, 23 insertions, 21 deletions
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 11babe1273..ec3888fa43 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -14,29 +14,9 @@ * GNU General Public License for more details. */ -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/32bit/entry32.inc> -#include <cpu/x86/fpu_enable.inc> -#if IS_ENABLED(CONFIG_SSE) -#include <cpu/x86/sse_enable.inc> -#endif +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) /* - * The assembly.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include <generated/assembly.inc> - -#else -/* * This path is for stages that post bootblock when employing * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc * as all those settings are cached within the processor. In order to @@ -65,4 +45,26 @@ _start: car_stage_entry: 1: jmp 1b + +#else + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <cpu/x86/fpu_enable.inc> +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * The assembly.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include <generated/assembly.inc> + #endif |