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-rw-r--r--src/arch/x86/include/arch/ioapic.h19
-rw-r--r--src/arch/x86/include/arch/smp/mpspec.h3
-rw-r--r--src/arch/x86/ioapic.c44
-rw-r--r--src/arch/x86/mpspec.c8
4 files changed, 38 insertions, 36 deletions
diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h
index 9dc2339dec..530128a580 100644
--- a/src/arch/x86/include/arch/ioapic.h
+++ b/src/arch/x86/include/arch/ioapic.h
@@ -4,24 +4,23 @@
#define __I386_ARCH_IOAPIC_H
#define IO_APIC_ADDR 0xfec00000
-#define VIO_APIC_VADDR ((u8 *)IO_APIC_ADDR)
#ifndef __ACPI__
#include <types.h>
-u8 get_ioapic_id(void *ioapic_base);
-u8 get_ioapic_version(void *ioapic_base);
+u8 get_ioapic_id(uintptr_t ioapic_base);
+u8 get_ioapic_version(uintptr_t ioapic_base);
-unsigned int ioapic_get_max_vectors(void *ioapic_base);
-void ioapic_set_max_vectors(void *ioapic_base, int mre_count);
-void ioapic_lock_max_vectors(void *ioapic_base);
+unsigned int ioapic_get_max_vectors(uintptr_t ioapic_base);
+void ioapic_set_max_vectors(uintptr_t ioapic_base, int mre_count);
+void ioapic_lock_max_vectors(uintptr_t ioapic_base);
-void setup_ioapic(void *ioapic_base, u8 ioapic_id);
-void register_new_ioapic(void *ioapic_base);
-void register_new_ioapic_gsi0(void *ioapic_base);
+void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id);
+void register_new_ioapic(uintptr_t ioapic_base);
+void register_new_ioapic_gsi0(uintptr_t ioapic_base);
-void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb);
+void ioapic_set_boot_config(uintptr_t ioapic_base, bool irq_on_fsb);
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags);
#endif
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 0b5ca47002..80ae7e8db4 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -6,6 +6,7 @@
#include <acpi/acpi.h>
#include <device/device.h>
#include <cpu/x86/lapic_def.h>
+#include <types.h>
/*
* Structure definitions for SMP machines following the
@@ -227,7 +228,7 @@ void smp_write_processor(struct mp_config_table *mc,
void smp_write_processors(struct mp_config_table *mc);
/* Call smp_write_ioapic() and return IOAPIC ID field. */
-u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, void *apicaddr);
+u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, uintptr_t apicaddr);
void smp_write_intsrc(struct mp_config_table *mc,
u8 irqtype, u16 irqflag, u8 srcbus, u8 srcbusirq,
diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
index df97a50cf5..863317fb28 100644
--- a/src/arch/x86/ioapic.c
+++ b/src/arch/x86/ioapic.c
@@ -5,6 +5,8 @@
#include <arch/ioapic.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
+#include <inttypes.h>
+#include <types.h>
#define ALL (0xff << 24)
#define NONE (0)
@@ -21,19 +23,19 @@
#define SMI (2 << 8)
#define INT (1 << 8)
-static u32 io_apic_read(void *ioapic_base, u32 reg)
+static u32 io_apic_read(uintptr_t ioapic_base, u32 reg)
{
- write32(ioapic_base, reg);
- return read32(ioapic_base + 0x10);
+ write32p(ioapic_base, reg);
+ return read32p(ioapic_base + 0x10);
}
-static void io_apic_write(void *ioapic_base, u32 reg, u32 value)
+static void io_apic_write(uintptr_t ioapic_base, u32 reg, u32 value)
{
- write32(ioapic_base, reg);
- write32(ioapic_base + 0x10, value);
+ write32p(ioapic_base, reg);
+ write32p(ioapic_base + 0x10, value);
}
-static void write_vector(void *ioapic_base, u8 vector, u32 high, u32 low)
+static void write_vector(uintptr_t ioapic_base, u8 vector, u32 high, u32 low)
{
io_apic_write(ioapic_base, vector * 2 + 0x10, low);
io_apic_write(ioapic_base, vector * 2 + 0x11, high);
@@ -44,7 +46,7 @@ static void write_vector(void *ioapic_base, u8 vector, u32 high, u32 low)
/* Bits 23-16 of register 0x01 specify the maximum redirection entry, which
* is the number of interrupts minus 1. */
-unsigned int ioapic_get_max_vectors(void *ioapic_base)
+unsigned int ioapic_get_max_vectors(uintptr_t ioapic_base)
{
u32 reg;
u8 count;
@@ -63,7 +65,7 @@ unsigned int ioapic_get_max_vectors(void *ioapic_base)
/* Set maximum number of redirection entries (MRE). It is write-once register
* for some chipsets, and a negative mre_count will lock it to the number
* of vectors read from the register. */
-void ioapic_set_max_vectors(void *ioapic_base, int mre_count)
+void ioapic_set_max_vectors(uintptr_t ioapic_base, int mre_count)
{
u32 reg;
u8 count;
@@ -77,17 +79,17 @@ void ioapic_set_max_vectors(void *ioapic_base, int mre_count)
io_apic_write(ioapic_base, 0x01, reg);
}
-void ioapic_lock_max_vectors(void *ioapic_base)
+void ioapic_lock_max_vectors(uintptr_t ioapic_base)
{
ioapic_set_max_vectors(ioapic_base, -1);
}
-static void clear_vectors(void *ioapic_base, u8 first, u8 last)
+static void clear_vectors(uintptr_t ioapic_base, u8 first, u8 last)
{
u32 low, high;
u8 i;
- printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %p\n", ioapic_base);
+ printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %" PRIxPTR "\n", ioapic_base);
low = INT_DISABLED;
high = NONE;
@@ -101,7 +103,7 @@ static void clear_vectors(void *ioapic_base, u8 first, u8 last)
}
}
-static void route_i8259_irq0(void *ioapic_base)
+static void route_i8259_irq0(uintptr_t ioapic_base)
{
u32 bsp_lapicid = lapicid();
u32 low, high;
@@ -123,11 +125,11 @@ static void route_i8259_irq0(void *ioapic_base)
}
}
-static void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
+static void set_ioapic_id(uintptr_t ioapic_base, u8 ioapic_id)
{
int i;
- printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n",
+ printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %" PRIxPTR "\n",
ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
@@ -141,7 +143,7 @@ static void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
}
-u8 get_ioapic_id(void *ioapic_base)
+u8 get_ioapic_id(uintptr_t ioapic_base)
{
/*
* According to 82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)
@@ -151,12 +153,12 @@ u8 get_ioapic_id(void *ioapic_base)
return (io_apic_read(ioapic_base, 0x00) >> 24) & 0xff;
}
-u8 get_ioapic_version(void *ioapic_base)
+u8 get_ioapic_version(uintptr_t ioapic_base)
{
return io_apic_read(ioapic_base, 0x01) & 0xff;
}
-void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb)
+void ioapic_set_boot_config(uintptr_t ioapic_base, bool irq_on_fsb)
{
if (irq_on_fsb) {
/*
@@ -173,19 +175,19 @@ void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb)
}
}
-void setup_ioapic(void *ioapic_base, u8 ioapic_id)
+void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id)
{
set_ioapic_id(ioapic_base, ioapic_id);
clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1);
route_i8259_irq0(ioapic_base);
}
-void register_new_ioapic_gsi0(void *ioapic_base)
+void register_new_ioapic_gsi0(uintptr_t ioapic_base)
{
setup_ioapic(ioapic_base, 0);
}
-void register_new_ioapic(void *ioapic_base)
+void register_new_ioapic(uintptr_t ioapic_base)
{
static u8 ioapic_id;
ioapic_id++;
diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c
index ac3fc79ba9..f5242d3d6e 100644
--- a/src/arch/x86/mpspec.c
+++ b/src/arch/x86/mpspec.c
@@ -11,8 +11,8 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <identity.h>
-#include <stdint.h>
#include <string.h>
+#include <types.h>
/* Initialize the specified "mc" struct with initial values. */
void mptable_init(struct mp_config_table *mc)
@@ -207,7 +207,7 @@ static void smp_write_bus(struct mp_config_table *mc,
* APIC Flags:EN, Address
*/
static void smp_write_ioapic(struct mp_config_table *mc,
- u8 id, u8 ver, void *apicaddr)
+ u8 id, u8 ver, uintptr_t apicaddr)
{
struct mpc_config_ioapic *mpc;
mpc = smp_next_mpc_entry(mc);
@@ -216,11 +216,11 @@ static void smp_write_ioapic(struct mp_config_table *mc,
mpc->mpc_apicid = id;
mpc->mpc_apicver = ver;
mpc->mpc_flags = MPC_APIC_USABLE;
- mpc->mpc_apicaddr = apicaddr;
+ mpc->mpc_apicaddr = (void *)apicaddr;
smp_add_mpc_entry(mc, sizeof(*mpc));
}
-u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, void *apicaddr)
+u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, uintptr_t apicaddr)
{
u8 id = get_ioapic_id(apicaddr);
u8 ver = get_ioapic_version(apicaddr);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 04:43:14 +0000