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-rw-r--r--src/arch/x86/include/arch/acpi.h27
-rw-r--r--src/arch/x86/include/arch/acpigen.h10
-rw-r--r--src/arch/x86/include/arch/bootblock_romcc.h6
-rw-r--r--src/arch/x86/include/arch/cbfs.h7
-rw-r--r--src/arch/x86/include/arch/interrupt.h3
-rw-r--r--src/arch/x86/include/arch/io.h37
-rw-r--r--src/arch/x86/include/arch/pirq_routing.h3
-rw-r--r--src/arch/x86/include/arch/smp/mpspec.h6
8 files changed, 65 insertions, 34 deletions
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 41c4fa75c8..95cd3ac8e2 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -4,7 +4,8 @@
* Copyright (C) 2004 SUSE LINUX AG
* Copyright (C) 2004 Nick Barker
* Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
+ * Raptor Engineering
* Copyright (C) 2016 Siemens AG
* (Written by Stefan Reinauer <stepan@coresystems.de>)
*
@@ -85,8 +86,9 @@ typedef struct acpi_gen_regaddr {
u8 bit_width; /* Register size in bits */
u8 bit_offset; /* Register bit offset */
union {
- u8 resv; /* Reserved in ACPI 2.0 - 2.0b */
- u8 access_size; /* Access size in ACPI 2.0c/3.0/4.0/5.0 */
+ u8 resv; /* Reserved in ACPI 2.0 - 2.0b */
+ u8 access_size; /* Access size in ACPI 2.0c/3.0/4.0/5.0
+ */
};
u32 addrl; /* Register address, low 32 bits */
u32 addrh; /* Register address, high 32 bits */
@@ -109,7 +111,7 @@ typedef struct acpi_gen_regaddr {
/* 0xc0-0xff: OEM defined */
/* Access size definitions for Generic address structure */
-#define ACPI_ACCESS_SIZE_UNDEFINED 0 /* Undefined (legacy reasons) */
+#define ACPI_ACCESS_SIZE_UNDEFINED 0 /* Undefined (legacy reasons) */
#define ACPI_ACCESS_SIZE_BYTE_ACCESS 1
#define ACPI_ACCESS_SIZE_WORD_ACCESS 2
#define ACPI_ACCESS_SIZE_DWORD_ACCESS 3
@@ -206,7 +208,9 @@ typedef struct acpi_srat_mem {
u32 length_low; /* Mem range length, low */
u32 length_high; /* Mem range length, high */
u32 resv1;
- u32 flags; /* Enable bit 0, hot pluggable bit 1; Non Volatile bit 2, other bits reserved to 0 */
+ u32 flags; /* Enable bit 0, hot pluggable bit 1; Non Volatile bit 2,
+ * other bits reserved to 0
+ */
u32 resv2[2];
} __attribute__ ((packed)) acpi_srat_mem_t;
@@ -551,7 +555,9 @@ typedef struct acpi_hest_esd {
u16 resv;
u8 flags;
u8 enabled;
- u32 prealloc_erecords; /* The number of error records to pre-allocate for this error source. */
+ u32 prealloc_erecords; /* The number of error records to
+ * pre-allocate for this error source.
+ */
u32 max_section_per_record;
} __attribute__ ((packed)) acpi_hest_esd_t;
@@ -635,11 +641,13 @@ void acpi_create_vfct(struct device *device,
unsigned long current));
void acpi_create_ivrs(acpi_ivrs_t *ivrs,
- unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current));
+ unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct,
+ unsigned long current));
#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
void acpi_create_hpet(acpi_hpet_t *hpet);
-unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp);
+unsigned long acpi_write_hpet(device_t device, unsigned long start,
+ acpi_rsdp_t *rsdp);
/* cpu/intel/speedstep/acpi.c */
void generate_cpu_entries(device_t device);
@@ -670,7 +678,8 @@ unsigned long acpi_create_dmar_drhd_ds_msi_hpet(unsigned long current,
void acpi_write_hest(acpi_hest_t *hest,
unsigned long (*acpi_fill_hest)(acpi_hest_t *hest));
-unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len);
+unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
+ acpi_hest_esd_t *esd, u16 type, void *data, u16 len);
void acpi_save_gnvs(u32 gnvs_address);
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index c70e4b9653..b08ce93536 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -2,7 +2,8 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
+ * Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -203,14 +204,15 @@ void acpigen_write_empty_PTC(void);
void acpigen_write_PRW(u32 wake, u32 level);
void acpigen_write_STA(uint8_t status);
void acpigen_write_TPC(const char *gnvs_tpc_limit);
-void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat,
- u32 control, u32 status);
+void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
+ u32 busmLat, u32 control, u32 status);
typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord;
void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
void acpigen_write_CST_package_entry(acpi_cstate_t *cstate);
void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries);
typedef enum { CSD_HW_ALL = 0xfe } CSD_coord;
-void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index);
+void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype,
+ u32 index);
void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list);
void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h
index 2e96d2a55f..d6962d69f8 100644
--- a/src/arch/x86/include/arch/bootblock_romcc.h
+++ b/src/arch/x86/include/arch/bootblock_romcc.h
@@ -49,8 +49,10 @@ static void bootblock_mainboard_init(void)
#if CONFIG_USE_OPTION_TABLE
static void sanitize_cmos(void)
{
- if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) {
- unsigned char *cmos_default = (unsigned char *)walkcbfs("cmos.default");
+ if (cmos_error() || !cmos_chksum_valid()
+ || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) {
+ unsigned char *cmos_default =
+ (unsigned char *)walkcbfs("cmos.default");
if (cmos_default) {
int i;
cmos_disable_rtc();
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index 81100a5476..54f0fa97e1 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -27,7 +27,8 @@ static struct cbfs_file *walkcbfs_head(char *target)
asm volatile (
"mov $1f, %%esp\n\t"
"jmp walkcbfs_asm\n\t"
- "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp");
+ "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi",
+ "esp");
return entry;
}
@@ -41,7 +42,9 @@ static void *walkcbfs(char *target)
return (void *)0;
}
-/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */
+/* just enough to support findstage. copied because the original version doesn't
+ * easily pass through romcc
+ */
struct cbfs_stage_restricted {
unsigned long compression;
unsigned long entry; // this is really 64bit, but properly endianized
diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h
index a3c1b3d823..90a29afd91 100644
--- a/src/arch/x86/include/arch/interrupt.h
+++ b/src/arch/x86/include/arch/interrupt.h
@@ -26,7 +26,8 @@ extern void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void));
#elif CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <device/oprom/yabel/biosemu.h>
#else
-static inline void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)) { }
+static inline void mainboard_interrupt_handlers(int intXX,
+ int (*intXX_func)(void)) { }
#endif
#endif /* INTERRUPT_H */
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index f16c09171a..c194379bb6 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -156,32 +156,38 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
);
}
-static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr)
+static inline __attribute__((always_inline)) uint8_t read8(
+ const volatile void *addr)
{
return *((volatile uint8_t *)(addr));
}
-static inline __attribute__((always_inline)) uint16_t read16(const volatile void *addr)
+static inline __attribute__((always_inline)) uint16_t read16(
+ const volatile void *addr)
{
return *((volatile uint16_t *)(addr));
}
-static inline __attribute__((always_inline)) uint32_t read32(const volatile void *addr)
+static inline __attribute__((always_inline)) uint32_t read32(
+ const volatile void *addr)
{
return *((volatile uint32_t *)(addr));
}
-static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
+static inline __attribute__((always_inline)) void write8(volatile void *addr,
+ uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write16(volatile void *addr, uint16_t value)
+static inline __attribute__((always_inline)) void write16(volatile void *addr,
+ uint16_t value)
{
*((volatile uint16_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value)
+static inline __attribute__((always_inline)) void write32(volatile void *addr,
+ uint32_t value)
{
*((volatile uint32_t *)(addr)) = value;
}
@@ -238,8 +244,8 @@ static inline int __ffs(u32 value)
/* Use pci_devfn_t or pnp_devfn_t instead */
typedef u32 device_t;
-/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
- * We don't need to set %fs, and %gs anymore
+/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write
+ * memory above 4G, We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
*/
@@ -301,7 +307,8 @@ void pci_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
}
#define PCI_DEV_INVALID (0xffffffffU)
-static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev)
+static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id,
+ pci_devfn_t dev)
{
for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
unsigned int id;
@@ -312,7 +319,8 @@ static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t
return PCI_DEV_INVALID;
}
-static inline pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
+static inline pci_devfn_t pci_locate_device(unsigned int pci_id,
+ pci_devfn_t dev)
{
for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
unsigned int id;
@@ -341,14 +349,16 @@ static inline pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id,
}
/* Generic functions for pnp devices */
-static inline __attribute__((always_inline)) void pnp_write_config(pnp_devfn_t dev, uint8_t reg, uint8_t value)
+static inline __attribute__((always_inline)) void pnp_write_config(
+ pnp_devfn_t dev, uint8_t reg, uint8_t value)
{
unsigned int port = dev >> 8;
outb(reg, port);
outb(value, port + 1);
}
-static inline __attribute__((always_inline)) uint8_t pnp_read_config(pnp_devfn_t dev, uint8_t reg)
+static inline __attribute__((always_inline)) uint8_t pnp_read_config(
+ pnp_devfn_t dev, uint8_t reg)
{
unsigned int port = dev >> 8;
outb(reg, port);
@@ -384,7 +394,8 @@ void pnp_set_iobase(pnp_devfn_t dev, unsigned int index, unsigned int iobase)
static inline __attribute__((always_inline))
uint16_t pnp_read_iobase(pnp_devfn_t dev, unsigned int index)
{
- return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1);
+ return ((uint16_t)(pnp_read_config(dev, index)) << 8)
+ | pnp_read_config(dev, index + 1);
}
static inline __attribute__((always_inline))
diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h
index d1390ba981..acd456b173 100644
--- a/src/arch/x86/include/arch/pirq_routing.h
+++ b/src/arch/x86/include/arch/pirq_routing.h
@@ -56,7 +56,8 @@ struct irq_routing_table {
struct irq_info slots[CONFIG_IRQ_SLOT_COUNT];
} __attribute__((packed));
-unsigned long copy_pirq_routing_table(unsigned long addr, const struct irq_routing_table *routing_table);
+unsigned long copy_pirq_routing_table(unsigned long addr,
+ const struct irq_routing_table *routing_table);
unsigned long write_pirq_routing_table(unsigned long start);
#if CONFIG_PIRQ_ROUTE
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 4123e7432c..4c80dbb45a 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -278,8 +278,10 @@ void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire);
unsigned long write_smp_table(unsigned long addr);
void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa);
-void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external);
-void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, int *isa_bus);
+void mptable_add_isa_interrupts(struct mp_config_table *mc,
+ unsigned long bus_isa, unsigned long apicid, int external);
+void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus,
+ int *isa_bus);
void *mptable_finalize(struct mp_config_table *mc);
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 03:13:05 +0000