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Diffstat (limited to 'src/arch/x86/car.ld')
-rw-r--r--src/arch/x86/car.ld17
1 files changed, 5 insertions, 12 deletions
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 5207157fe9..5a46b8b2ec 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -11,9 +11,7 @@
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
* aligned when using this option. */
- _pagetables = . ;
- . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
- _epagetables = . ;
+ REGION(pagetables, ., 4K * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4K)
#endif
#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
/* Vboot work buffer only needs to be available when verified boot
@@ -28,9 +26,7 @@
/* Stack for CAR stages. Since it persists across all stages that
* use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */
- _car_stack = .;
- . += CONFIG_DCACHE_BSP_STACK_SIZE;
- _ecar_stack = .;
+ REGION(car_stack, ., CONFIG_DCACHE_BSP_STACK_SIZE, 4)
/* The pre-ram cbmem console as well as the timestamp region are fixed
* in size. Therefore place them above the car global section so that
* multiple stages (romstage and verstage) have a consistent
@@ -42,9 +38,7 @@
* totalling 32 bytes that need to be 32-byte aligned. The reason the
* pdpt are not colocated with the rest of the page tables is to reduce
* fragmentation of the CAR space that persists across stages. */
- _pdpt = .;
- . += 32;
- _epdpt = .;
+ REGION(pdpt, ., 32, 32)
#endif
TIMESTAMP(., 0x200)
@@ -56,10 +50,8 @@
FMAP_CACHE(., FMAP_SIZE)
#endif
- _car_ehci_dbg_info = .;
/* Reserve sizeof(struct ehci_dbg_info). */
- . += 80;
- _ecar_ehci_dbg_info = .;
+ REGION(car_ehci_dbg_info, ., 80, 1)
/* _bss and _ebss provide symbols to per-stage
* variables that are not shared like the timestamp and the pre-ram
@@ -75,6 +67,7 @@
*(.sbss.*)
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_ebss = .;
+ RECORD_SIZE(bss)
#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)
_shadow_size = (_ebss - _car_region_start) >> 3;