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-rw-r--r--src/arch/ppc/boot/coreboot_table.c2
-rw-r--r--src/arch/ppc/include/arch/cpu.h16
-rw-r--r--src/arch/ppc/include/arch/io.h24
-rw-r--r--src/arch/ppc/include/arch/pirq_routing.h8
-rw-r--r--src/arch/ppc/init/crt0.S.lb20
-rw-r--r--src/arch/ppc/init/ldscript.lb18
-rw-r--r--src/arch/ppc/lib/pci_dev.c24
-rw-r--r--src/arch/ppc/lib/printk_init.c6
8 files changed, 59 insertions, 59 deletions
diff --git a/src/arch/ppc/boot/coreboot_table.c b/src/arch/ppc/boot/coreboot_table.c
index b1420a7491..dc154b2a71 100644
--- a/src/arch/ppc/boot/coreboot_table.c
+++ b/src/arch/ppc/boot/coreboot_table.c
@@ -340,7 +340,7 @@ unsigned long write_coreboot_table(
head = lb_table_init(low_table_end);
low_table_end = (unsigned long)head;
- if (HAVE_OPTION_TABLE == 1) {
+ if (CONFIG_HAVE_OPTION_TABLE == 1) {
struct lb_record *rec_dest, *rec_src;
/* Write the option config table... */
rec_dest = lb_new_record(head);
diff --git a/src/arch/ppc/include/arch/cpu.h b/src/arch/ppc/include/arch/cpu.h
index e0ed4ff66a..3026486420 100644
--- a/src/arch/ppc/include/arch/cpu.h
+++ b/src/arch/ppc/include/arch/cpu.h
@@ -13,24 +13,24 @@ struct cpu_driver {
struct cpu_device_id *id_table;
};
-#ifndef STACK_SIZE
-#error STACK_SIZE not defined
+#ifndef CONFIG_STACK_SIZE
+#error CONFIG_STACK_SIZE not defined
#endif
/* The basic logic comes from the Linux kernel.
- * The invariant is that (1 << 31 - STACK_BITS) == STACK_SIZE
+ * The invariant is that (1 << 31 - STACK_BITS) == CONFIG_STACK_SIZE
* I wish there was simpler way to support multiple stack sizes.
* Oh well.
*/
-#if STACK_SIZE == 4096
+#if CONFIG_STACK_SIZE == 4096
#define STACK_BITS "19"
-#elif STACK_SIZE == 8192
+#elif CONFIG_STACK_SIZE == 8192
#define STACK_BITS "18"
-#elif STACK_SIZE == 16384
+#elif CONFIG_STACK_SIZE == 16384
#define STACK_BITS "17"
-#elif STACK_SIZE == 32768
+#elif CONFIG_STACK_SIZE == 32768
#define STACK_BITS "16"
-#elif STACK_SIZE == 65536
+#elif CONFIG_STACK_SIZE == 65536
#define STACK_BITS "15"
#else
#error Unimplemented stack size
diff --git a/src/arch/ppc/include/arch/io.h b/src/arch/ppc/include/arch/io.h
index fd0d1e4654..ba8ce4fa85 100644
--- a/src/arch/ppc/include/arch/io.h
+++ b/src/arch/ppc/include/arch/io.h
@@ -11,8 +11,8 @@
#define SLOW_DOWN_IO
-#ifndef _IO_BASE
-#define _IO_BASE 0
+#ifndef CONFIG_IO_BASE
+#define CONFIG_IO_BASE 0
#endif
#define readb(addr) in_8((volatile uint8_t *)(addr))
@@ -36,15 +36,15 @@
* are arrays of bytes, and byte-swapping is not appropriate in
* that case. - paulus
*/
-#define insw(port, buf, ns) _insw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns))
-#define outsw(port, buf, ns) _outsw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns) _insw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns) _outsw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
-#define inb(port) in_8((uint8_t *)((port)+_IO_BASE))
-#define outb(val, port) out_8((uint8_t *)((port)+_IO_BASE), (val))
-#define inw(port) in_le16((uint16_t *)((port)+_IO_BASE))
-#define outw(val, port) out_le16((uint16_t *)((port)+_IO_BASE), (val))
-#define inl(port) in_le32((uint32_t *)((port)+_IO_BASE))
-#define outl(val, port) out_le32((uint32_t *)((port)+_IO_BASE), (val))
+#define inb(port) in_8((uint8_t *)((port)+CONFIG_IO_BASE))
+#define outb(val, port) out_8((uint8_t *)((port)+CONFIG_IO_BASE), (val))
+#define inw(port) in_le16((uint16_t *)((port)+CONFIG_IO_BASE))
+#define outw(val, port) out_le16((uint16_t *)((port)+CONFIG_IO_BASE), (val))
+#define inl(port) in_le32((uint32_t *)((port)+CONFIG_IO_BASE))
+#define outl(val, port) out_le32((uint32_t *)((port)+CONFIG_IO_BASE), (val))
#define inb_p(port) inb((port))
#define outb_p(val, port) outb((val), (port))
@@ -56,8 +56,8 @@
/*
* The *_ns versions below do byte-swapping.
*/
-#define insw_ns(port, buf, ns) _insw((uint16_t *)((port)+_IO_BASE), (buf), (ns))
-#define outsw_ns(port, buf, ns) _outsw((uint16_t *)((port)+_IO_BASE), (buf), (ns))
+#define insw_ns(port, buf, ns) _insw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns) _outsw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
#define IO_SPACE_LIMIT ~0
diff --git a/src/arch/ppc/include/arch/pirq_routing.h b/src/arch/ppc/include/arch/pirq_routing.h
index dad8531eb5..00c9556319 100644
--- a/src/arch/ppc/include/arch/pirq_routing.h
+++ b/src/arch/ppc/include/arch/pirq_routing.h
@@ -16,8 +16,8 @@ struct irq_info {
u8 rfu;
} __attribute__((packed));
-#if defined(IRQ_SLOT_COUNT)
-#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT
+#if defined(CONFIG_IRQ_SLOT_COUNT)
+#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT
#elif (__GNUC__ < 3)
#define IRQ_SLOTS_COUNT 1
#else
@@ -39,13 +39,13 @@ struct irq_routing_table {
extern const struct irq_routing_table intel_irq_routing_table;
-#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE)
+#if defined(CONFIG_DEBUG) && defined(CONFIG_HAVE_PIRQ_TABLE)
void check_pirq_routing_table(void);
#else
#define check_pirq_routing_table() do {} while(0)
#endif
-#if defined(HAVE_PIRQ_TABLE)
+#if defined(CONFIG_HAVE_PIRQ_TABLE)
unsigned long copy_pirq_routing_table(unsigned long start);
#else
#define copy_pirq_routing_table(start) (start)
diff --git a/src/arch/ppc/init/crt0.S.lb b/src/arch/ppc/init/crt0.S.lb
index 738d4b4a67..bbccc59213 100644
--- a/src/arch/ppc/init/crt0.S.lb
+++ b/src/arch/ppc/init/crt0.S.lb
@@ -30,8 +30,8 @@ system_reset:
*/
%%PROCESSOR_INIT%%
-#if USE_DCACHE_RAM == 1
-#define DCACHE_RAM_END (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1)
+#if CONFIG_USE_DCACHE_RAM == 1
+#define DCACHE_RAM_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
/*
* Initialize data cache blocks
* (assumes cache block size of 32 bytes)
@@ -39,9 +39,9 @@ system_reset:
* NOTE: This may need to be moved to FAMILY_INIT if
* dcbz is not supported on all CPU's
*/
- lis r1, DCACHE_RAM_BASE@h
- ori r1, r1, DCACHE_RAM_BASE@l
- li r3, (DCACHE_RAM_SIZE / 32)
+ lis r1, CONFIG_DCACHE_RAM_BASE@h
+ ori r1, r1, CONFIG_DCACHE_RAM_BASE@l
+ li r3, (CONFIG_DCACHE_RAM_SIZE / 32)
mtctr r3
0: dcbz r0, r1
addi r1, r1, 32
@@ -53,8 +53,8 @@ system_reset:
* it 16-byte aligned to cover both cases. Also we have to ensure that
* the first word is located within the cache.
*/
- lis r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@h
- ori r1, r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@l
+ lis r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@h
+ ori r1, r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@l
lis r0, 0
stwu r0, -4(r1)
stwu r0, -4(r1)
@@ -65,8 +65,8 @@ system_reset:
/*
* Clear stack
*/
- lis r4, DCACHE_RAM_BASE@h
- ori r4, r4, DCACHE_RAM_BASE@l
+ lis r4, CONFIG_DCACHE_RAM_BASE@h
+ ori r4, r4, CONFIG_DCACHE_RAM_BASE@l
lis r7, DCACHE_RAM_END@h
ori r7, r7, DCACHE_RAM_END@l
lis r5, 0
@@ -110,7 +110,7 @@ system_reset:
* Complete rest of initialization in C (ppc_main)
*/
rfi
-#endif /* USE_DCACHE_RAM */
+#endif /* CONFIG_USE_DCACHE_RAM */
/*
* Stop here if something goes wrong
diff --git a/src/arch/ppc/init/ldscript.lb b/src/arch/ppc/init/ldscript.lb
index a81d9b9bb8..453c99c13b 100644
--- a/src/arch/ppc/init/ldscript.lb
+++ b/src/arch/ppc/init/ldscript.lb
@@ -1,14 +1,14 @@
/*
* Memory map:
*
- * _ROMBASE : start of ROM
- * _RESET : reset vector (may be at top of ROM)
+ * CONFIG_ROMBASE : start of ROM
+ * CONFIG_RESET : reset vector (may be at top of ROM)
* _EXCEPTIONS_VECTORS : exception table
*
- * _ROMSTART : coreboot text
+ * CONFIG_ROMSTART : coreboot text
* : payload text
*
- * _RAMBASE : address to copy payload
+ * CONFIG_RAMBASE : address to copy payload
*/
/*
@@ -32,13 +32,13 @@ SECTIONS
/*
* Absolute location of base of ROM
*/
- . = _ROMBASE;
+ . = CONFIG_ROMBASE;
/*
* Absolute location of reset vector. This may actually be at the
* the top of ROM.
*/
- . = _RESET;
+ . = CONFIG_RESET;
.reset . : {
*(.rom.reset);
. = ALIGN(16);
@@ -47,7 +47,7 @@ SECTIONS
/*
* Absolute location of exception vector table.
*/
- . = _EXCEPTION_VECTORS;
+ . = CONFIG_EXCEPTION_VECTORS;
.exception_vectors . : {
*(.rom.exception_vectors);
. = ALIGN(16);
@@ -56,7 +56,7 @@ SECTIONS
/*
* Absolute location of coreboot initialization code in ROM.
*/
- . = _ROMSTART;
+ . = CONFIG_ROMSTART;
.rom . : {
_rom = .;
*(.rom.text);
@@ -94,7 +94,7 @@ SECTIONS
/*
* Absolute location of where coreboot will be relocated in RAM.
*/
- _iseg = _RAMBASE;
+ _iseg = CONFIG_RAMBASE;
_eiseg = _iseg + SIZEOF(.ram);
_liseg = _ram;
_eliseg = _eram;
diff --git a/src/arch/ppc/lib/pci_dev.c b/src/arch/ppc/lib/pci_dev.c
index adb047e3fe..d821f17c77 100644
--- a/src/arch/ppc/lib/pci_dev.c
+++ b/src/arch/ppc/lib/pci_dev.c
@@ -9,8 +9,8 @@ uint8_t pci_ppc_read_config8(unsigned char bus, int devfn, int where)
{
uint8_t res;
- out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- res = in_8((unsigned char *)PCIC0_CFGDATA + (where & 3));
+ out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+ res = in_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3));
return res;
}
@@ -18,8 +18,8 @@ uint16_t pci_ppc_read_config16(unsigned char bus, int devfn, int where)
{
uint16_t res;
- out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- res = in_le16((unsigned short *)PCIC0_CFGDATA + (where & 2));
+ out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+ res = in_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2));
return res;
}
@@ -27,28 +27,28 @@ uint32_t pci_ppc_read_config32(unsigned char bus, int devfn, int where)
{
uint32_t res;
- out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- res = in_le32((unsigned *)PCIC0_CFGDATA);
+ out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+ res = in_le32((unsigned *)CONFIG_PCIC0_CFGDATA);
return res;
}
int pci_ppc_write_config8(unsigned char bus, int devfn, int where, uint8_t data)
{
- out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- out_8((unsigned char *)PCIC0_CFGDATA + (where & 3), data);
+ out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+ out_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3), data);
return 0;
}
int pci_ppc_write_config16(unsigned char bus, int devfn, int where, uint16_t data)
{
- out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- out_le16((unsigned short *)PCIC0_CFGDATA + (where & 2), data);
+ out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+ out_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2), data);
return 0;
}
int pci_ppc_write_config32(unsigned char bus, int devfn, int where, uint32_t data)
{
- out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- out_le32((unsigned *)PCIC0_CFGDATA, data);
+ out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+ out_le32((unsigned *)CONFIG_PCIC0_CFGDATA, data);
return 0;
}
diff --git a/src/arch/ppc/lib/printk_init.c b/src/arch/ppc/lib/printk_init.c
index 401d271391..98d78b3fc4 100644
--- a/src/arch/ppc/lib/printk_init.c
+++ b/src/arch/ppc/lib/printk_init.c
@@ -12,7 +12,7 @@
/* Keep together for sysctl support */
-int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
extern int vtxprintf(void (*)(unsigned char), const char *, va_list);
extern void uart8250_tx_byte(unsigned, unsigned char);
@@ -20,8 +20,8 @@ extern void uart8250_tx_byte(unsigned, unsigned char);
void console_tx_byte(unsigned char byte)
{
if (byte == '\n')
- uart8250_tx_byte(TTYS0_BASE, '\r');
- uart8250_tx_byte(TTYS0_BASE, byte);
+ uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r');
+ uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
}
int do_printk(int msg_level, const char *fmt, ...)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-15 19:54:14 +0000