diff options
Diffstat (limited to 'src/arch/ppc/include')
| -rw-r--r-- | src/arch/ppc/include/ppc4xx.h | 11 | ||||
| -rwxr-xr-x | src/arch/ppc/include/ppc74xx.h | 32 | ||||
| -rwxr-xr-x | src/arch/ppc/include/ppc750.h | 33 | ||||
| -rw-r--r-- | src/arch/ppc/include/ppc970.h | 30 | ||||
| -rw-r--r-- | src/arch/ppc/include/ppcreg.h | 86 |
5 files changed, 131 insertions, 61 deletions
diff --git a/src/arch/ppc/include/ppc4xx.h b/src/arch/ppc/include/ppc4xx.h index 279e1aa161..48066cedc2 100644 --- a/src/arch/ppc/include/ppc4xx.h +++ b/src/arch/ppc/include/ppc4xx.h @@ -68,6 +68,17 @@ #define sprg6w 0x116 /* Special purpose general 6 - write only */ #define sprg7w 0x117 /* Special purpose general 7 - write only */ +/*----------------------------------------------------------------------------+ +| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1, ++----------------------------------------------------------------------------*/ +#define MSR_APE 0x00080000 /* wait state enable */ +#define MSR_WE 0x00040000 /* wait state enable */ +#define MSR_CE 0x00020000 /* critical interrupt enable */ +#define MSR_DWE 0x00000400 /* debug wait enable */ +#define MSR_DE 0x00000200 /* debug interrupt enable */ +#define MSR_IR 0x00000020 /* instruction relocale */ +#define MSR_DR 0x00000010 /* data relocale */ + /****************************************************************************** * Special for PPC405GP ******************************************************************************/ diff --git a/src/arch/ppc/include/ppc74xx.h b/src/arch/ppc/include/ppc74xx.h new file mode 100755 index 0000000000..121efbe28d --- /dev/null +++ b/src/arch/ppc/include/ppc74xx.h @@ -0,0 +1,32 @@ +/* We are interested in the following hid0 bits: + 6 - ECLK - Enable external test clock (603 only) + 11 - DPM - Turn on dynamic power management (603 only) + 15 - NHR - Not hard reset + 16 - ICE - Instruction cache enable + 17 - DCE - Data cache enable + 18 - ILOCK - Instruction cache lock + 19 - DLOCK - Data cache lock + 20 - ICFI - Instruction cache invalidate + 21 - DCFI - Data cache invalidate + 24 - NOSER - Serial execution disable (604 only - turbo mode) + 24 - SGE - Store gathering enable (7410 only) + 29 - BHT - Branch history table (604 only) + + I made up the tags for the 604 specific bits, as they aren't + named in the 604 book. The 603 book calls the invalidate bits + ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named + one, and Motorola named the other. */ + +#define HID0_ECLK 0x02000000 +#define HID0_DPM 0x00100000 +#define HID0_NHR 0x00010000 +#define HID0_ICE 0x00008000 +#define HID0_DCE 0x00004000 +#define HID0_ILOCK 0x00002000 +#define HID0_DLOCK 0x00001000 +#define HID0_ICFI 0x00000800 +#define HID0_DCFI 0x00000400 +#define HID0_NOSER 0x00000080 +#define HID0_SGE 0x00000080 +#define HID0_BTIC 0x00000020 +#define HID0_BHT 0x00000004 diff --git a/src/arch/ppc/include/ppc750.h b/src/arch/ppc/include/ppc750.h new file mode 100755 index 0000000000..05fa37e894 --- /dev/null +++ b/src/arch/ppc/include/ppc750.h @@ -0,0 +1,33 @@ +/* We are interested in the following hid0 bits: + 6 - ECLK - Enable external test clock (603 only) + 11 - DPM - Turn on dynamic power management (603 only) + 15 - NHR - Not hard reset + 16 - ICE - Instruction cache enable + 17 - DCE - Data cache enable + 18 - ILOCK - Instruction cache lock + 19 - DLOCK - Data cache lock + 20 - ICFI - Instruction cache invalidate + 21 - DCFI - Data cache invalidate + 24 - NOSER - Serial execution disable (604 only - turbo mode) + 24 - SGE - Store gathering enable (7410 only) + 29 - BHT - Branch history table (604 only) + + I made up the tags for the 604 specific bits, as they aren't + named in the 604 book. The 603 book calls the invalidate bits + ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named + one, and Motorola named the other. */ + +#define HID0_ECLK 0x02000000 +#define HID0_DPM 0x00100000 +#define HID0_NHR 0x00010000 +#define HID0_ICE 0x00008000 +#define HID0_DCE 0x00004000 +#define HID0_ILOCK 0x00002000 +#define HID0_DLOCK 0x00001000 +#define HID0_ICFI 0x00000800 +#define HID0_DCFI 0x00000400 +#define HID0_NOSER 0x00000080 +#define HID0_SGE 0x00000080 +#define HID0_BTIC 0x00000020 +#define HID0_BHT 0x00000004 + diff --git a/src/arch/ppc/include/ppc970.h b/src/arch/ppc/include/ppc970.h index 7358d52e44..5c0f884972 100644 --- a/src/arch/ppc/include/ppc970.h +++ b/src/arch/ppc/include/ppc970.h @@ -18,16 +18,30 @@ | 13-Oct-03 Created MPT +----------------------------------------------------------------------------*/ -#ifndef _sys_as_archppc970_h_ -#define _sys_as_archppc970_h_ +#ifndef _PPC970_H_ +#define _PPC970_H_ /*----------------------------------------------------------------------------+ -| PVR value. +| When timers are running based on CPU speed this is the timer to CPU frequency +| ratio. +----------------------------------------------------------------------------*/ -#define PVR_970_DD1 0x00391100 -#define PVR_970FX_DD2 0x003C0200 -#define PVR_970FX_DD2_1 0x003C0201 -#define PVR_970FX_DD3 0x003C0300 +#define PPC970_TB_RATIO 8 + +/*----------------------------------------------------------------------------+ +| Cache line size. ++----------------------------------------------------------------------------*/ +#define CACHE_LINE_SIZE_L1 128 +#define CACHE_LINE_SIZE_L2 128 + +/*----------------------------------------------------------------------------+ +| SLB size. ++----------------------------------------------------------------------------*/ +#define SLB_SIZE 64 + +/*----------------------------------------------------------------------------+ +| TLB size. ++----------------------------------------------------------------------------*/ +#define TLB_SIZE 1024 /*----------------------------------------------------------------------------+ | Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64) @@ -225,4 +239,4 @@ #define SRR1_ITLB_RELOA 0x00000000000C0000 #define SRR1_RI 0x0000000000000002 -#endif /* _sys_as_archppc970_h_ */ +#endif /* _PPC970_H_ */ diff --git a/src/arch/ppc/include/ppcreg.h b/src/arch/ppc/include/ppcreg.h index a778a49377..e6bb752b6d 100644 --- a/src/arch/ppc/include/ppcreg.h +++ b/src/arch/ppc/include/ppcreg.h @@ -2,78 +2,25 @@ /* This code is distributed without warranty under the GPL v2 (see COPYING) */ /* In the MSR, not all bits are interesting to us - 13 - POW - Power management - 14 - TGPR - temporary registers for page table routines - 15 - ILE - Exception little endian 16 - EE - External interrupts 17 - PR - Privilege level 18 - FP - Floating Point available 19 - ME - Machine check exception enable 20 - FE0 - Floating exception mode 0 - 21 - SE - Single step trace mode - 22 - BE - Branch trace enable 23 - FE1 - Floating exception mode 1 - 25 - IP - Exception prefix - 26 - IR - Instruction address translation - 27 - DR - Data address translation - 30 - RI - Recoverable exception - 31 - LE - Little endian mode MSR_MASK is the bits we do not change. */ #define MSR_MASK 0xfff8008c -#define MSR_POW 0x00040000 -#define MSR_TGPR 0x00020000 -#define MSR_ILE 0x00010000 #define MSR_EE 0x00008000 #define MSR_PR 0x00004000 #define MSR_FP 0x00002000 #define MSR_ME 0x00001000 #define MSR_FE0 0x00000800 -#define MSR_SE 0x00000400 -#define MSR_BE 0x00000200 #define MSR_FE1 0x00000100 -#define MSR_IP 0x00000040 -#define MSR_IR 0x00000020 -#define MSR_DR 0x00000010 -#define MSR_RI 0x00000002 -#define MSR_LE 0x00000001 #define MSR_DEFAULT (MSR_FP | MSR_IR | MSR_DR) -/* We are interested in the following hid0 bits: - 6 - ECLK - Enable external test clock (603 only) - 11 - DPM - Turn on dynamic power management (603 only) - 15 - NHR - Not hard reset - 16 - ICE - Instruction cache enable - 17 - DCE - Data cache enable - 18 - ILOCK - Instruction cache lock - 19 - DLOCK - Data cache lock - 20 - ICFI - Instruction cache invalidate - 21 - DCFI - Data cache invalidate - 24 - NOSER - Serial execution disable (604 only - turbo mode) - 24 - SGE - Store gathering enable (7410 only) - 29 - BHT - Branch history table (604 only) - - I made up the tags for the 604 specific bits, as they aren't - named in the 604 book. The 603 book calls the invalidate bits - ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named - one, and Motorola named the other. */ - -#define HID0_ECLK 0x02000000 -#define HID0_DPM 0x00100000 -#define HID0_NHR 0x00010000 -#define HID0_ICE 0x00008000 -#define HID0_DCE 0x00004000 -#define HID0_ILOCK 0x00002000 -#define HID0_DLOCK 0x00001000 -#define HID0_ICFI 0x00000800 -#define HID0_DCFI 0x00000400 -#define HID0_NOSER 0x00000080 -#define HID0_SGE 0x00000080 -#define HID0_BTIC 0x00000020 -#define HID0_BHT 0x00000004 - /* * BAT defines */ @@ -181,6 +128,39 @@ #define PVR_8240 0x00810100 #define PVR_8260 PVR_8240 +/*----------------------------------------------------------------------------+ +| Processor Version Register (PVR) values ++----------------------------------------------------------------------------*/ +#define PVR_970 0x0039 /* 970 any revision*/ +#define PVR_970DD_1_0 0x00391100 /* 970 DD1.0 */ +#define PVR_970FX 0x003C /* 970FX any revision*/ +#define PVR_970FX_DD_2_0 0x003C0200 /* 970FX DD2.0 */ +#define PVR_970FX_DD_2_1 0x003C0201 /* 970FX DD2.1 */ +#define PVR_970FX_DD_3_0 0x003C0300 /* 970FX DD3.0 */ +#define PVR_RESERVED 0x000000F0 /* reserved nibble */ + +#define SPR_SRR0 0x01a +#define SPR_SRR1 0x01b +#define SPR_SPRG0 0x110 +#define SPR_SPRG1 0x111 +#define SPR_SPRG2 0x112 +#define SPR_SPRG3 0x113 +#define SPR_PVR 0x11f +#define SPR_TBLR 0x10c +#define SPR_TBUR 0x10d + +#ifdef __PPC64__ +#define LOAD_64BIT_VAL(ra,value) addis ra,r0,value@highest; \ + ori ra,ra,value@higher; \ + sldi ra,ra,32; \ + oris ra,ra,value@h; \ + ori ra,ra,value@l +#define TLBIEL(rb) .long 0x7C000000|\ + (rb<<11)|(274<<1) +#define HRFID() .long 0x4C000000|\ + (274<<1) +#endif + #ifndef ASM unsigned __getmsr(void); void __setmsr(unsigned value); |