diff options
Diffstat (limited to 'src/arch/i386')
-rw-r--r-- | src/arch/i386/Makefile.inc | 27 | ||||
-rw-r--r-- | src/arch/i386/coreboot_apc.ld | 100 | ||||
-rw-r--r-- | src/arch/i386/init/ldscript_apc.lb | 7 |
3 files changed, 25 insertions, 109 deletions
diff --git a/src/arch/i386/Makefile.inc b/src/arch/i386/Makefile.inc index e9d651c1e9..d1cb806049 100644 --- a/src/arch/i386/Makefile.inc +++ b/src/arch/i386/Makefile.inc @@ -22,12 +22,16 @@ endif ifeq ($(CONFIG_BOOTSPLASH),y) COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_FALLBACK_BOOTSPLASH_FILE) endif +ifeq ($(CONFIG_AP_CODE_IN_CAR),y) +COREBOOT_ROM_DEPENDENCIES+=$(obj)/coreboot_ap +endif + $(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp - if [ -f fallback/coreboot_apc ]; \ + if [ -f $(obj)/coreboot_ap ]; \ then \ - $(CBFSTOOL) $@.tmp add-stage fallback/coreboot_apc $(CONFIG_CBFS_PREFIX)/coreboot_apc $(CBFS_COMPRESS_FLAG); \ + $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ap $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ fi $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @@ -81,6 +85,19 @@ $(obj)/coreboot.a: $$(objs) $(AR) cr $(obj)/coreboot.a $^ ####################################################################### +# coreboot_ap.rom + +ifeq ($(CONFIG_AP_CODE_IN_CAR),y) + +$(obj)/coreboot_ap: $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/i386/init/ldscript_apc.lb $^ + $(NM) -n $(obj)/coreboot_ap | sort > $(obj)/coreboot_ap.map + + +endif + +####################################################################### # done crt0s = @@ -174,10 +191,6 @@ ifeq ($(CONFIG_MMX),y) crt0s += $(src)/cpu/x86/mmx_disable.inc endif -ifeq ($(CONFIG_AP_CODE_IN_CAR),y) -ldscripts += $(src)/arch/i386/init/ldscript_apc.lb -endif - ifeq ($(CONFIG_BIG_BOOTBLOCK),y) crt0s += $(chipset_bootblock_inc) ldscripts += $(chipset_bootblock_lds) @@ -198,7 +211,7 @@ else $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@ + $(CC) -MMD $(CFLAGS) -I$(src) -I. -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h printf " CC romstage.inc\n" diff --git a/src/arch/i386/coreboot_apc.ld b/src/arch/i386/coreboot_apc.ld deleted file mode 100644 index d7820aafe1..0000000000 --- a/src/arch/i386/coreboot_apc.ld +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Memory map: - * - * CONFIG_DCACHE_RAM_BASE - * : data segment - * : bss segment - * : heap - * : stack - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling - * 2006.05 yhlu tailed it to use it for AP code in cache - */ -/* - * We use ELF as output format. So that we can - * debug the code in some form. - */ -INCLUDE ldoptions - -ENTRY(_start) - -SECTIONS -{ - . = CONFIG_DCACHE_RAM_BASE; - /* - * First we place the code and read only data (typically const declared). - * This get placed in rom. - */ - .text : { - _text = .; - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } - .rodata : { - _rodata = .; - . = ALIGN(4); - *(.rodata) - *(.rodata.*) - . = ALIGN(4); - _erodata = .; - } - /* - * After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } - /* - * bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - _bss = .; - .bss . : { - *(.bss) - *(.sbss) - *(COMMON) - } - _ebss = .; - _end = .; - . = ALIGN(0x1000); - _stack = .; - .stack . : { - . = 0x4000; - } - _estack = .; - _heap = .; - .heap . : { - . = ALIGN(4); - } - _eheap = .; - /* The ram segment - * This is all address of the memory resident copy of coreboot. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - _bogus = ASSERT( ( _eram_seg <= ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big"); - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} diff --git a/src/arch/i386/init/ldscript_apc.lb b/src/arch/i386/init/ldscript_apc.lb index 2c8cb84e63..1e79c0aa6f 100644 --- a/src/arch/i386/init/ldscript_apc.lb +++ b/src/arch/i386/init/ldscript_apc.lb @@ -1,9 +1,12 @@ -INPUT(coreboot_apc.rom) +/* INPUT(coreboot_ap.rom)*/ +INCLUDE "ldoptions" SECTIONS { .apcrom . : { _apcrom = .; - coreboot_apc.rom(*) + *(.text) + *(.rodata) + *(.rodata.*) _eapcrom = .; } _iseg_apc = CONFIG_DCACHE_RAM_BASE; |