diff options
Diffstat (limited to 'src/arch/i386')
-rw-r--r-- | src/arch/i386/include/arch/mmio_conf.h | 67 | ||||
-rw-r--r-- | src/arch/i386/include/arch/pci_ops.h | 4 | ||||
-rw-r--r-- | src/arch/i386/include/arch/pciconf.h | 5 | ||||
-rw-r--r-- | src/arch/i386/include/arch/romcc_io.h | 116 | ||||
-rw-r--r-- | src/arch/i386/lib/Config.lb | 6 | ||||
-rw-r--r-- | src/arch/i386/lib/console.c | 2 | ||||
-rw-r--r-- | src/arch/i386/lib/pci_ops_conf1.c | 4 | ||||
-rw-r--r-- | src/arch/i386/lib/pci_ops_mmconf.c | 63 |
8 files changed, 263 insertions, 4 deletions
diff --git a/src/arch/i386/include/arch/mmio_conf.h b/src/arch/i386/include/arch/mmio_conf.h new file mode 100644 index 0000000000..df91cb561d --- /dev/null +++ b/src/arch/i386/include/arch/mmio_conf.h @@ -0,0 +1,67 @@ +#ifndef ARCH_MMIO_H +#define ARCH_MMIO_H 1 + + +//extended read, GS is already set + +static inline __attribute__((always_inline)) uint8_t read8x(uint32_t addr) +{ + uint8_t value; + __asm__ volatile ( + "movb %%gs:(%1), %0\n\t" + :"=a"(value): "b" (addr) + ); + return value; +} + +static inline __attribute__((always_inline)) uint16_t read16x(uint32_t addr) +{ + uint16_t value; + __asm__ volatile ( + "movw %%gs:(%1), %0\n\t" + :"=a"(value): "b" (addr) + ); + + return value; + +} + +static inline __attribute__((always_inline)) uint32_t read32x(uint32_t addr) +{ + uint32_t value; + __asm__ volatile ( + "movl %%gs:(%1), %0\n\t" + :"=a"(value): "b" (addr) + ); + + return value; + +} + +static inline __attribute__((always_inline)) void write8x(uint32_t addr, uint8_t value) +{ + __asm__ volatile ( + "movb %1, %%gs:(%0)\n\t" + :: "b" (addr), "a" (value) + ); + +} + +static inline __attribute__((always_inline)) void write16x(uint32_t addr, uint16_t value) +{ + __asm__ volatile ( + "movw %1, %%gs:(%0)\n\t" + :: "b" (addr), "a" (value) + ); + +} + +static inline __attribute__((always_inline)) void write32x(uint32_t addr, uint32_t value) +{ + __asm__ volatile ( + "movl %1, %%gs:(%0)\n\t" + :: "b" (addr), "a" (value) + ); +} + +#endif /* ARCH_MMIO_H */ diff --git a/src/arch/i386/include/arch/pci_ops.h b/src/arch/i386/include/arch/pci_ops.h index 72307a6211..5972df1d72 100644 --- a/src/arch/i386/include/arch/pci_ops.h +++ b/src/arch/i386/include/arch/pci_ops.h @@ -4,6 +4,10 @@ const struct pci_bus_operations pci_cf8_conf1; const struct pci_bus_operations pci_cf8_conf2; +#if MMCONF_SUPPORT==1 +const struct pci_bus_operations pci_ops_mmconf; +#endif + void pci_set_method(device_t dev); #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/arch/i386/include/arch/pciconf.h b/src/arch/i386/include/arch/pciconf.h index 8695ee2294..5887522c8b 100644 --- a/src/arch/i386/include/arch/pciconf.h +++ b/src/arch/i386/include/arch/pciconf.h @@ -4,6 +4,11 @@ // inclusive of ANYTHING that uses a PCI bus. #define PCI_CONF_REG_INDEX 0xcf8 #define PCI_CONF_REG_DATA 0xcfc + +#if PCI_IO_CFG_EXT == 0 #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) +#else +#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) ) +#endif #endif diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h index 6fafbd99a9..6cb6a767d9 100644 --- a/src/arch/i386/include/arch/romcc_io.h +++ b/src/arch/i386/include/arch/romcc_io.h @@ -34,6 +34,12 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui *((volatile uint32_t *)(addr)) = value; } +#if MMCONF_SUPPORT + +#include <arch/mmio_conf.h> + +#endif + static inline int log2(int value) { unsigned int r = 0; @@ -76,87 +82,193 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) -typedef unsigned device_t; +typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ + +/* FIXME: We need to make the LinuxBIOS to run at 64bit mode, So when read/write memory above 4G, + * We don't need to set %fs, and %gs anymore + * Before that We need to use %gs, and leave %fs to other RAM access + */ static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 +#endif outl(0x80000000 | (addr & ~3), 0xCF8); return inb(0xCFC + (addr & 3)); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + return read8x(addr); +} +#endif static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) { +#if MMCONF_SUPPORT + return pci_mmio_read_config8(dev, where); +#else return pci_io_read_config8(dev, where); +#endif } static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); return inw(0xCFC + (addr & 2)); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + return read16x(addr); +} +#endif + static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) { +#if MMCONF_SUPPORT + return pci_mmio_read_config16(dev, where); +#else return pci_io_read_config16(dev, where); +#endif } static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + return read32x(addr); +} +#endif + static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) { +#if MMCONF_SUPPORT + return pci_mmio_read_config32(dev, where); +#else return pci_io_read_config32(dev, where); +#endif } static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); outb(value, 0xCFC + (addr & 3)); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) +{ + unsigned addr; + addr = dev | where; + write8x(addr, value); +} +#endif + static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) { +#if MMCONF_SUPPORT + pci_mmio_write_config8(dev, where, value); +#else pci_io_write_config8(dev, where, value); +#endif } static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); outw(value, 0xCFC + (addr & 2)); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) +{ + unsigned addr; + addr = dev | where; + write16x(addr, value); +} +#endif + static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) { +#if MMCONF_SUPPORT + pci_mmio_write_config16(dev, where, value); +#else pci_io_write_config16(dev, where, value); +#endif } static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) +{ + unsigned addr; + addr = dev | where; + write32x(addr, value); +} +#endif + static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) { +#if MMCONF_SUPPORT + pci_mmio_write_config32(dev, where, value); +#else pci_io_write_config32(dev, where, value); +#endif } #define PCI_DEV_INVALID (0xffffffffU) @@ -174,7 +286,7 @@ static device_t pci_io_locate_device(unsigned pci_id, device_t dev) static device_t pci_locate_device(unsigned pci_id, device_t dev) { - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + for(; dev <= PCI_DEV(255|(((1<<PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); if (id == pci_id) { diff --git a/src/arch/i386/lib/Config.lb b/src/arch/i386/lib/Config.lb index 023c0312ff..e7d895ccc2 100644 --- a/src/arch/i386/lib/Config.lb +++ b/src/arch/i386/lib/Config.lb @@ -1,13 +1,17 @@ uses CONFIG_USE_INIT +uses CONFIG_USE_PRINTK_IN_CAR object c_start.S object cpu.c object pci_ops_conf1.c object pci_ops_conf2.c +object pci_ops_mmconf.c object pci_ops_auto.c object exception.c if CONFIG_USE_INIT - initobject printk_init.o + if CONFIG_USE_PRINTK_IN_CAR + initobject printk_init.o + end end diff --git a/src/arch/i386/lib/console.c b/src/arch/i386/lib/console.c index a1f5d6f2a4..262a0db2f4 100644 --- a/src/arch/i386/lib/console.c +++ b/src/arch/i386/lib/console.c @@ -1,6 +1,6 @@ #include <console/loglevel.h> -#if CONFIG_USE_INIT == 0 +#if CONFIG_USE_PRINTK_IN_CAR == 0 static void __console_tx_byte(unsigned char byte) { uart_tx_byte(byte); diff --git a/src/arch/i386/lib/pci_ops_conf1.c b/src/arch/i386/lib/pci_ops_conf1.c index b4181e39bc..4c4cd672e6 100644 --- a/src/arch/i386/lib/pci_ops_conf1.c +++ b/src/arch/i386/lib/pci_ops_conf1.c @@ -8,7 +8,11 @@ * Functions for accessing PCI configuration space with type 1 accesses */ +#if PCI_IO_CFG_EXT == 0 #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3)) +#else +#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) ) +#endif static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where) { diff --git a/src/arch/i386/lib/pci_ops_mmconf.c b/src/arch/i386/lib/pci_ops_mmconf.c new file mode 100644 index 0000000000..5095c31cd7 --- /dev/null +++ b/src/arch/i386/lib/pci_ops_mmconf.c @@ -0,0 +1,63 @@ +#if MMCONF_SUPPORT + +#include <console/console.h> +#include <arch/io.h> +#include <arch/pciconf.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + + +/* + * Functions for accessing PCI configuration space with mmconf accesses + */ + +#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEVFN) & 0xFF) << 12) | \ + ((WHERE) & 0xFFF)) + +#include <arch/mmio_conf.h> + +static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int where) +{ + return (read8x(PCI_MMIO_ADDR(bus, devfn, where))); +} + +static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where) +{ + return (read16x(PCI_MMIO_ADDR(bus, devfn, where))); +} + +static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where) +{ + return (read32x(PCI_MMIO_ADDR(bus, devfn, where))); +} + +static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) +{ + write8x(PCI_MMIO_ADDR(bus, devfn, where), value); +} + +static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) +{ + write8x(PCI_MMIO_ADDR(bus, devfn, where), value); +} + +static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) +{ + write8x(PCI_MMIO_ADDR(bus, devfn, where), value); +} + + +const struct pci_bus_operations pci_ops_mmconf = +{ + .read8 = pci_mmconf_read_config8, + .read16 = pci_mmconf_read_config16, + .read32 = pci_mmconf_read_config32, + .write8 = pci_mmconf_write_config8, + .write16 = pci_mmconf_write_config16, + .write32 = pci_mmconf_write_config32, +}; + +#endif |