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-rw-r--r--src/arch/i386/Kconfig59
-rw-r--r--src/arch/i386/Makefile.inc98
-rw-r--r--src/arch/i386/boot/Makefile.inc10
-rw-r--r--src/arch/i386/init/Makefile.inc1
-rw-r--r--src/arch/i386/lib/Makefile.inc15
-rw-r--r--src/arch/i386/smp/Makefile.inc5
6 files changed, 188 insertions, 0 deletions
diff --git a/src/arch/i386/Kconfig b/src/arch/i386/Kconfig
new file mode 100644
index 0000000000..ce36f55e92
--- /dev/null
+++ b/src/arch/i386/Kconfig
@@ -0,0 +1,59 @@
+config ARCH_X86
+ boolean
+ help
+ This option is used to set the architecture of a mainboard.
+ It is usually set in mainboard/*/Kconfig.
+
+config ARCH
+ string
+ default i386
+ depends on ARCH_X86
+ help
+ This is the name of the respective subdirectory in arch/.
+
+config ROMBASE
+ hex
+ default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+ default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+ default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+ default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+ default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+
+config PAYLOAD_SIZE
+ hex
+ default 0
+
+config ROM_PAYLOAD_START
+ hex
+ default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+ default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+ default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+ default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+ default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+
+config ROM_IMAGE_SIZE
+ hex
+ default 0x200000 if COREBOOT_ROMSIZE_KB_2048
+ default 0x100000 if COREBOOT_ROMSIZE_KB_1024
+ default 0x80000 if COREBOOT_ROMSIZE_KB_512
+ default 0x40000 if COREBOOT_ROMSIZE_KB_256
+ default 0x20000 if COREBOOT_ROMSIZE_KB_128
+
+config RAMBASE
+ hex
+ default 0x100000
+
+config STACK_SIZE
+ hex
+ default 0x8000
+
+
+menu "Misc Options"
+
+config MAX_REBOOT_CNT
+ int "Maximum Reboot Count"
+ default 3
+
+endmenu
+
+
diff --git a/src/arch/i386/Makefile.inc b/src/arch/i386/Makefile.inc
new file mode 100644
index 0000000000..4195183f8d
--- /dev/null
+++ b/src/arch/i386/Makefile.inc
@@ -0,0 +1,98 @@
+#######################################################################
+# Take care of subdirectories
+subdirs-y += boot
+subdirs-y += init
+subdirs-y += lib
+subdirs-y += smp
+
+obj-y += ../../option_table.o
+
+ifdef POST_EVALUATION
+#######################################################################
+# Build the final rom image
+
+$(obj)/coreboot.rom: $(obj)/coreboot.bootblock $(obj)/coreboot_ram $(CBFSTOOL)
+ $(Q)rm -f $@
+ $(Q)$(CBFSTOOL) $@ create $(shell expr 1024 \* $(CONFIG_COREBOOT_ROMSIZE_KB)) 131072 $(obj)/coreboot.bootblock
+ $(Q)$(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram normal/coreboot_ram $(CBFS_COMPRESS_FLAG)
+ $(Q)if [ -f fallback/coreboot_apc ]; \
+ then \
+ $(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \
+ fi
+ $(Q)$(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram fallback/coreboot_ram $(CBFS_COMPRESS_FLAG)
+ifeq ($(CONFIG_PAYLOAD_NONE),y)
+ $(Q)printf " PAYLOAD none (as specified by user)\n"
+else
+ printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
+ $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_COMPRESS_FLAG)
+ printf " PAYLOAD $(CONFIG_NORMAL_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
+ $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_NORMAL_PAYLOAD_FILE) normal/payload $(CBFS_COMPRESS_FLAG)
+ $(CBFSTOOL) ./build/coreboot.rom print
+endif
+
+
+#######################################################################
+# Build the bootblock
+
+BOOTBLOCK_SIZE=65536
+
+$(obj)/coreboot.bootblock: $(obj)/coreboot.strip
+ $(Q)printf " CREATE $(subst $(obj)/,,$(@))\n"
+ $(Q)dd if=$< of=$(obj)/coreboot.bootblock.one obs=$(BOOTBLOCK_SIZE) conv=sync
+ $(Q)cat $(obj)/coreboot.bootblock.one $(obj)/coreboot.bootblock.one > $(obj)/coreboot.bootblock
+
+$(obj)/coreboot.strip: $(obj)/coreboot
+ $(Q)printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
+ $(Q)$(OBJCOPY) -O binary $< $@
+
+$(obj)/ldscript.ld: $(ldscripts) $(obj)/ldoptions
+ $(Q)printf 'INCLUDE "ldoptions"\n' > $@
+ $(Q)printf '$(foreach ldscript,$(ldscripts),INCLUDE "$(ldscript)"\n)' >> $@
+
+$(obj)/crt0_includes.h: $(crt0s)
+ $(Q)printf '$(foreach crt0,$(obj)/config.h $(crt0s),#include "$(crt0)"\n)' > $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s
+ $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm
+
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h
+ $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@
+
+$(obj)/coreboot: $(initobjs) $(obj)/ldscript.ld
+ $(Q)printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/ldscript.ld $(initobjs)
+ $(Q)$(NM) -n $(obj)/coreboot | sort > $(obj)/coreboot.map
+
+#######################################################################
+# i386 specific tools
+
+$(obj)/option_table.h $(obj)/option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
+ $(Q)printf " OPTION $(subst $(obj)/,,$(@))\n"
+ $(Q)$(obj)/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $(obj)/option_table.h --option $(obj)/option_table.c
+
+$(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h
+ $(Q)printf " HOSTCC $(subst $(obj)/,,$(@))\n"
+ $(Q)$(HOSTCC) $(HOSTCFLAGS) -include $(obj)/config.h $< -o $@
+
+#######################################################################
+# Build the coreboot_ram (stage 2)
+
+$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/config/coreboot_ram.ld #ldoptions
+ $(Q)printf " CC $(subst $(obj)/,,$(@))\n"
+ $(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/config/coreboot_ram.ld $(obj)/coreboot_ram.o
+ $(Q)$(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map
+
+$(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
+ $(Q)printf " CC $(subst $(obj)/,,$(@))\n"
+ $(Q)$(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,-\( $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)
+
+$(obj)/coreboot.a: $(objs)
+ $(Q)printf " AR $(subst $(obj)/,,$(@))\n"
+ $(Q)rm -f $(obj)/coreboot.a
+ $(Q)$(AR) cr $(obj)/coreboot.a $(objs)
+
+
+#######################################################################
+# done
+
+endif
diff --git a/src/arch/i386/boot/Makefile.inc b/src/arch/i386/boot/Makefile.inc
new file mode 100644
index 0000000000..40bb3b8e13
--- /dev/null
+++ b/src/arch/i386/boot/Makefile.inc
@@ -0,0 +1,10 @@
+
+obj-y += boot.o
+obj-y += coreboot_table.o
+obj-$(CONFIG_MULTIBOOT) += multiboot.o
+obj-y += tables.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += pirq_routing.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.o
+obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
+
diff --git a/src/arch/i386/init/Makefile.inc b/src/arch/i386/init/Makefile.inc
new file mode 100644
index 0000000000..792d600548
--- /dev/null
+++ b/src/arch/i386/init/Makefile.inc
@@ -0,0 +1 @@
+#
diff --git a/src/arch/i386/lib/Makefile.inc b/src/arch/i386/lib/Makefile.inc
new file mode 100644
index 0000000000..a1cf617fb2
--- /dev/null
+++ b/src/arch/i386/lib/Makefile.inc
@@ -0,0 +1,15 @@
+obj-y += c_start.o
+obj-y += cpu.o
+obj-y += pci_ops_conf1.o
+obj-y += pci_ops_conf2.o
+obj-y += pci_ops_mmconf.o
+obj-y += pci_ops_auto.o
+obj-y += exception.o
+
+initobj-y += printk_init.o
+initobj-y += cbfs_and_run.o
+
+ifdef POST_EVALUATION
+$(obj)/arch/i386/lib/console.o :: $(obj)/build.h
+endif
+
diff --git a/src/arch/i386/smp/Makefile.inc b/src/arch/i386/smp/Makefile.inc
new file mode 100644
index 0000000000..119dd6d40e
--- /dev/null
+++ b/src/arch/i386/smp/Makefile.inc
@@ -0,0 +1,5 @@
+obj-$(CONFIG_HAVE_MP_TABLE) += mpspec.o
+# what about this: how awkward.
+#object ioapic.o CONFIG_IOAPIC
+
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 06:42:09 +0000