18 files changed, 0 insertions, 1219 deletions

diff --git a/src/arch/armv7/include/arch/boot/boot.h b/src/arch/armv7/include/arch/boot/boot.h
deleted file mode 100644
index 08651cd1a8..0000000000
--- a/src/arch/armv7/include/arch/boot/boot.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef ASM_ARM_BOOT_H
-#define ASM_ARM_BOOT_H
-
-#define ELF_CLASS	ELFCLASS32
-#define ELF_DATA	ELFDATA2LSB
-#define ELF_ARCH	EM_ARM
-
-#endif /* ASM_ARM_BOOT_H */
diff --git a/src/arch/armv7/include/arch/byteorder.h b/src/arch/armv7/include/arch/byteorder.h
deleted file mode 100644
index 8dc069f486..0000000000
--- a/src/arch/armv7/include/arch/byteorder.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _BYTEORDER_H
-#define _BYTEORDER_H
-
-#define __LITTLE_ENDIAN 1234
-
-#include <stdint.h>
-#include <swab.h>
-
-#define cpu_to_le64(x) ((uint64_t)(x))
-#define le64_to_cpu(x) ((uint64_t)(x))
-#define cpu_to_le32(x) ((uint32_t)(x))
-#define le32_to_cpu(x) ((uint32_t)(x))
-#define cpu_to_le16(x) ((uint16_t)(x))
-#define le16_to_cpu(x) ((uint16_t)(x))
-#define cpu_to_be64(x) swab64(x)
-#define be64_to_cpu(x) swab64(x)
-#define cpu_to_be32(x) swab32((x))
-#define be32_to_cpu(x) swab32((x))
-#define cpu_to_be16(x) swab16((x))
-#define be16_to_cpu(x) swab16((x))
-
-#define ntohll(x) be64_to_cpu(x)
-#define htonll(x) cpu_to_be64(x)
-#define ntohl(x)  be32_to_cpu(x)
-#define htonl(x)  cpu_to_be32(x)
-
-#endif /* _BYTEORDER_H */
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
deleted file mode 100644
index 1cd9958fc4..0000000000
--- a/src/arch/armv7/include/arch/cache.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * cache.h: Cache maintenance API for ARMv7
- */
-
-#ifndef ARMV7_CACHE_H
-#define ARMV7_CACHE_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* SCTLR bits */
-#define SCTLR_M		(1 << 0)	/* MMU enable			*/
-#define SCTLR_A		(1 << 1)	/* Alignment check enable	*/
-#define SCTLR_C		(1 << 2)	/* Data/unified cache enable	*/
-/* Bits 4:3 are reserved */
-#define SCTLR_CP15BEN	(1 << 5)	/* CP15 barrier enable		*/
-/* Bit 6 is reserved */
-#define SCTLR_B		(1 << 7)	/* Endianness			*/
-/* Bits 9:8 */
-#define SCTLR_SW	(1 << 10)	/* SWP and SWPB enable		*/
-#define SCTLR_Z		(1 << 11)	/* Branch prediction enable	*/
-#define SCTLR_I		(1 << 12)	/* Instruction cache enable	*/
-#define SCTLR_V		(1 << 13)	/* Low/high exception vectors 	*/
-#define SCTLR_RR  	(1 << 14)	/* Round Robin select		*/
-/* Bits 16:15 are reserved */
-#define SCTLR_HA	(1 << 17)	/* Hardware Access flag enable	*/
-/* Bit 18 is reserved */
-/* Bits 20:19 reserved virtualization not supported */
-#define SCTLR_WXN	(1 << 19)	/* Write permission implies XN	*/
-#define SCTLR_UWXN	(1 << 20)	/* Unprivileged write permission
-					   implies PL1 XN		*/
-#define SCTLR_FI	(1 << 21)	/* Fast interrupt config enable	*/
-#define SCTLR_U		(1 << 22)	/* Unaligned access behavior	*/
-#define SCTLR_VE	(1 << 24)	/* Interrupt vectors enable	*/
-#define SCTLR_EE	(1 << 25)	/* Exception endianness		*/
-/* Bit 26 is reserved */
-#define SCTLR_NMFI	(1 << 27)	/* Non-maskable FIQ support	*/
-#define SCTLR_TRE	(1 << 28)	/* TEX remap enable		*/
-#define SCTLR_AFE	(1 << 29)	/* Access flag enable		*/
-#define SCTLR_TE	(1 << 30)	/* Thumb exception enable	*/
-/* Bit 31 is reserved */
-
-/*
- * Sync primitives
- */
-
-/* data memory barrier */
-static inline void dmb(void)
-{
-	asm volatile ("dmb" : : : "memory");
-}
-
-/* data sync barrier */
-static inline void dsb(void)
-{
-	asm volatile ("dsb" : : : "memory");
-}
-
-/* instruction sync barrier */
-static inline void isb(void)
-{
-	asm volatile ("isb" : : : "memory");
-}
-
-/*
- * Low-level TLB maintenance operations
- */
-
-/* invalidate entire data TLB */
-static inline void dtlbiall(void)
-{
-	asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory");
-}
-
-/* invalidate entire instruction TLB */
-static inline void itlbiall(void)
-{
-	asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
-}
-
-/* invalidate entire unified TLB */
-static inline void tlbiall(void)
-{
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
-}
-
-/* invalidate unified TLB by MVA, all ASID */
-static inline void tlbimvaa(unsigned long mva)
-{
-	asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory");
-}
-
-/* write data access control register (DACR) */
-static inline void write_dacr(uint32_t val)
-{
-	asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val));
-}
-
-/* write translation table base register 0 (TTBR0) */
-static inline void write_ttbr0(uint32_t val)
-{
-	asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
-}
-
-/* read translation table base control register (TTBCR) */
-static inline uint32_t read_ttbcr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val));
-	return val;
-}
-
-/* write translation table base control register (TTBCR) */
-static inline void write_ttbcr(uint32_t val)
-{
-	asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory");
-}
-
-/*
- * Low-level cache maintenance operations
- */
-
-/* branch predictor invalidate all */
-static inline void bpiall(void)
-{
-	asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
-}
-
-/* data cache clean and invalidate by MVA to PoC */
-static inline void dccimvac(unsigned long mva)
-{
-	asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva) : "memory");
-}
-
-/* data cache invalidate by set/way */
-static inline void dccisw(uint32_t val)
-{
-	asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val) : "memory");
-}
-
-/* data cache clean by MVA to PoC */
-static inline void dccmvac(unsigned long mva)
-{
-	asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
-}
-
-/* data cache clean by set/way */
-static inline void dccsw(uint32_t val)
-{
-	asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory");
-}
-
-/* data cache invalidate by MVA to PoC */
-static inline void dcimvac(unsigned long mva)
-{
-	asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva) : "memory");
-}
-
-/* data cache invalidate by set/way */
-static inline void dcisw(uint32_t val)
-{
-	asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val) : "memory");
-}
-
-/* instruction cache invalidate all by PoU */
-static inline void iciallu(void)
-{
-	asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
-}
-
-/*
- * Cache co-processor (CP15) access functions
- */
-
-/* read cache level ID register (CLIDR) */
-static inline uint32_t read_clidr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val));
-	return val;
-}
-
-/* read cache size ID register register (CCSIDR) */
-static inline uint32_t read_ccsidr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
-	return val;
-}
-
-/* read cache size selection register (CSSELR) */
-static inline uint32_t read_csselr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val));
-	return val;
-}
-
-/* write to cache size selection register (CSSELR) */
-static inline void write_csselr(uint32_t val)
-{
-	/*
-	 * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
-	 * Bit 0 - 0 = data or unified cache, 1 = instruction cache
-	 */
-	asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val));
-	isb();	/* ISB to sync the change to CCSIDR */
-}
-
-/* read L2 control register (L2CTLR) */
-static inline uint32_t read_l2ctlr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
-	return val;
-}
-
-/* write L2 control register (L2CTLR) */
-static inline void write_l2ctlr(uint32_t val)
-{
-	/*
-	 * Note: L2CTLR can only be written when the L2 memory system
-	 * is idle, ie before the MMU is enabled.
-	 */
-	asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
-	isb();
-}
-
-/* read L2 Auxiliary Control Register (L2ACTLR) */
-static inline uint32_t read_l2actlr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
-	return val;
-}
-
-/* write L2 Auxiliary Control Register (L2ACTLR) */
-static inline void write_l2actlr(uint32_t val)
-{
-	asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
-	isb();
-}
-
-/* read system control register (SCTLR) */
-static inline uint32_t read_sctlr(void)
-{
-	uint32_t val;
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
-	return val;
-}
-
-/* write system control register (SCTLR) */
-static inline void write_sctlr(uint32_t val)
-{
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc");
-	isb();
-}
-
-/*
- * Cache maintenance API
- */
-
-/* dcache clean and invalidate all (on current level given by CCSELR) */
-void dcache_clean_invalidate_all(void);
-
-/* dcache clean by modified virtual address to PoC */
-void dcache_clean_by_mva(void const *addr, size_t len);
-
-/* dcache clean and invalidate by modified virtual address to PoC */
-void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
-
-/* dcache invalidate by modified virtual address to PoC */
-void dcache_invalidate_by_mva(void const *addr, size_t len);
-
-void dcache_clean_all(void);
-
-/* dcache invalidate all (on current level given by CCSELR) */
-void dcache_invalidate_all(void);
-
-/* dcache and MMU disable */
-void dcache_mmu_disable(void);
-
-/* dcache and MMU enable */
-void dcache_mmu_enable(void);
-
-/* icache invalidate all (on current level given by CSSELR) */
-void icache_invalidate_all(void);
-
-/* tlb invalidate all */
-void tlb_invalidate_all(void);
-
-/*
- * Generalized setup/init functions
- */
-
-/* invalidate all caches on ARMv7 */
-void armv7_invalidate_caches(void);
-
-/* mmu initialization (set page table address, set permissions, etc) */
-void mmu_init(void);
-
-enum dcache_policy {
-	DCACHE_OFF,
-	DCACHE_WRITEBACK,
-	DCACHE_WRITETHROUGH,
-};
-
-/* disable the mmu for a range. Primarily useful to lock out address 0. */
-void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
-/* mmu range configuration (set dcache policy) */
-void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
-						enum dcache_policy policy);
-
-#endif /* ARMV7_CACHE_H */
diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h
deleted file mode 100644
index 52cc8a3f50..0000000000
--- a/src/arch/armv7/include/arch/cpu.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#ifndef __ARCH_CPU_H__
-#define __ARCH_CPU_H__
-
-#define asmlinkage
-
-#if !defined(__PRE_RAM__)
-#include <device/device.h>
-
-struct cpu_driver {
-	struct device_operations *ops;
-	struct cpu_device_id *id_table;
-};
-
-struct thread;
-
-struct cpu_info {
-	device_t cpu;
-	unsigned long index;
-#if CONFIG_COOP_MULTITASKING
-	struct thread *thread;
-#endif
-};
-
-struct cpuinfo_arm {
-        uint8_t    arm;            /* CPU family */
-        uint8_t    arm_vendor;     /* CPU vendor */
-        uint8_t    arm_model;
-};
-
-#endif
-
-/* Primitives for CPU and MP cores. */
-
-/* read Main Id register (MIDR) */
-inline static uint32_t read_midr(void)
-{
-	uint32_t value;
-	asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r"(value));
-	return value;
-}
-
-/* read Multiprocessor Affinity Register (MPIDR) */
-inline static uint32_t read_mpidr(void)
-{
-	uint32_t value;
-	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r"(value));
-	return value;
-}
-
-/* read Auxiliary Control Register (ACTLR) */
-inline static uint32_t read_actlr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val));
-	return val;
-}
-
-/* write Auxiliary Control Register (ACTLR) */
-inline static void write_actlr(uint32_t val)
-{
-	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (val));
-}
-
-/* wait for interrupt. */
-inline static void wfi(void)
-{
-	asm volatile ("wfi" : : : "memory");
-}
-
-/* wait for event. */
-inline static void wfe(void)
-{
-	asm volatile ("wfe");
-}
-
-/* set event (to bring up cores in WFE state). */
-inline static void sev(void)
-{
-	asm volatile ("sev");
-}
-
-/* puts CPU into System mode and disable interrupts. */
-inline static void set_system_mode(void)
-{
-	asm volatile("msr cpsr_c, %0" :: "r"(0x1f | 0xc0));
-}
-
-struct cpu_info *cpu_info(void);
-#endif /* __ARCH_CPU_H__ */
diff --git a/src/arch/armv7/include/arch/early_variables.h b/src/arch/armv7/include/arch/early_variables.h
deleted file mode 100644
index cec0a46239..0000000000
--- a/src/arch/armv7/include/arch/early_variables.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#ifndef ARCH_EARLY_VARIABLES_H
-#define ARCH_EARLY_VARIABLES_H
-
-#ifdef __PRE_RAM__
-#define CAR_GLOBAL __attribute__((section(".car.global_data")))
-#define CAR_CBMEM __attribute__((section(".car.cbmem_console")))
-#else
-#define CAR_GLOBAL
-#define CAR_CBMEM
-#endif
-
-#if defined(__PRE_RAM__)
-#define CAR_MIGRATE_ATTR __attribute__ ((used,section (".car.migrate")))
-
-/* Call migrate_fn_() when CAR globals are migrated. */
-#define CAR_MIGRATE(migrate_fn_) \
-	static void (* const migrate_fn_ ## _ptr)(void) CAR_MIGRATE_ATTR = \
-	migrate_fn_;
-
-/* Get the correct pointer for the CAR global variable. */
-void *car_get_var_ptr(void *var);
-
-/* Get and set a primitive type global variable. */
-#define car_get_var(var) \
-	*(typeof(var) *)car_get_var_ptr(&(var))
-#define car_set_var(var, val) \
-	do { car_get_var(var) = (val); } while(0)
-
-/* Migrate the CAR variables to memory. */
-void car_migrate_variables(void);
-
-#else
-#define CAR_MIGRATE(migrate_fn_)
-static inline void *car_get_var_ptr(void *var) { return var; }
-#define car_get_var(var) (var)
-#define car_set_var(var, val) do { (var) = (val); } while (0)
-static inline void car_migrate_variables(void) { }
-#endif
-
-#endif
diff --git a/src/arch/armv7/include/arch/exception.h b/src/arch/armv7/include/arch/exception.h
deleted file mode 100644
index 57076bd57b..0000000000
--- a/src/arch/armv7/include/arch/exception.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the libpayload project.
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _ARCH_EXCEPTION_H
-#define _ARCH_EXCEPTION_H
-
-#include <stdint.h>
-
-void exception_init(void);
-void set_vbar(uint32_t vbar);
-
-#endif
diff --git a/src/arch/armv7/include/arch/hlt.h b/src/arch/armv7/include/arch/hlt.h
deleted file mode 100644
index 285b6f8786..0000000000
--- a/src/arch/armv7/include/arch/hlt.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef ARCH_HLT_H
-#define ARCH_HLT_H
-
-static inline __attribute__((always_inline)) void hlt(void)
-{
-	for (;;) ;
-}
-
-#endif /* ARCH_HLT_H */
diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h
deleted file mode 100644
index e044090e68..0000000000
--- a/src/arch/armv7/include/arch/io.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Originally imported from linux/include/asm-arm/io.h. This file has changed
- * substantially since then.
- *
- *  Copyright 2013 Google Inc.
- *  Copyright (C) 1996-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Modifications:
- *  08-Apr-2013	G	Replaced several macros with inlines for type safety.
- *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
- *			constant addresses and variable addresses.
- *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
- *			specific IO header files.
- *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
- *  04-Apr-1999	PJB	Added check_signature.
- *  12-Dec-1999	RMK	More cleanups
- *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
- */
-#ifndef __ASM_ARM_IO_H
-#define __ASM_ARM_IO_H
-
-#include <types.h>
-#include <arch/cache.h>		/* for dmb() */
-#include <arch/byteorder.h>
-
-static inline uint8_t read8(const void *addr)
-{
-	dmb();
-	return *(volatile uint8_t *)addr;
-}
-
-static inline uint16_t read16(const void *addr)
-{
-	dmb();
-	return *(volatile uint16_t *)addr;
-}
-
-static inline uint32_t read32(const void *addr)
-{
-	dmb();
-	return *(volatile uint32_t *)addr;
-}
-
-static inline void write8(uint8_t val, void *addr)
-{
-	dmb();
-	*(volatile uint8_t *)addr = val;
-	dmb();
-}
-
-static inline void write16(uint16_t val, void *addr)
-{
-	dmb();
-	*(volatile uint16_t *)addr = val;
-	dmb();
-}
-
-static inline void write32(uint32_t val, void *addr)
-{
-	dmb();
-	*(volatile uint32_t *)addr = val;
-	dmb();
-}
-
-/*
- * FIXME: These are to avoid breaking existing ARM code. We should eventually
- * re-factor all code to specify the data length intended.
-  */
-#define readb(a)	read8(a)
-#define writeb(v,a)	write8(v,a)
-#define readl(a)	read32(a)
-#define writel(v,a)	write32(v,a)
-
-/*
- * Clear and set bits in one shot. These macros can be used to clear and
- * set multiple bits in a register using a single call. These macros can
- * also be used to set a multiple-bit bit pattern using a mask, by
- * specifying the mask in the 'clear' parameter and the new bit pattern
- * in the 'set' parameter.
- */
-
-#define out_arch(type,endian,a,v)	write##type(cpu_to_##endian(v),a)
-#define in_arch(type,endian,a)		endian##_to_cpu(read##type(a))
-
-#define out_le32(a,v)	out_arch(l,le32,a,v)
-#define out_le16(a,v)	out_arch(w,le16,a,v)
-
-#define in_le32(a)	in_arch(l,le32,a)
-#define in_le16(a)	in_arch(w,le16,a)
-
-#define out_be32(a,v)	out_arch(l,be32,a,v)
-#define out_be16(a,v)	out_arch(w,be16,a,v)
-
-#define in_be32(a)	in_arch(l,be32,a)
-#define in_be16(a)	in_arch(w,be16,a)
-
-#define out_8(a,v)	writeb(v,a)
-#define in_8(a)		readb(a)
-
-#define clrbits(type, addr, clear) \
-	out_##type((addr), in_##type(addr) & ~(clear))
-
-#define setbits(type, addr, set) \
-	out_##type((addr), in_##type(addr) | (set))
-
-#define clrsetbits(type, addr, clear, set) \
-	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
-
-#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
-#define setbits_be32(addr, set) setbits(be32, addr, set)
-#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
-
-#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
-#define setbits_le32(addr, set) setbits(le32, addr, set)
-#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
-
-#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
-#define setbits_be16(addr, set) setbits(be16, addr, set)
-#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
-
-#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
-#define setbits_le16(addr, set) setbits(le16, addr, set)
-#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
-
-#define clrbits_8(addr, clear) clrbits(8, addr, clear)
-#define setbits_8(addr, set) setbits(8, addr, set)
-#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
-
-#endif	/* __ASM_ARM_IO_H */
diff --git a/src/arch/armv7/include/arch/pci_ops.h b/src/arch/armv7/include/arch/pci_ops.h
deleted file mode 100644
index 7a7ed32a67..0000000000
--- a/src/arch/armv7/include/arch/pci_ops.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef ARCH_ARMV7_PCI_OPS_H
-#define ARCH_ARMV7_PCI_OPS_H
-
-/* Empty stub until PCI includes are properly fixed. */
-
-#endif
diff --git a/src/arch/armv7/include/arch/stages.h b/src/arch/armv7/include/arch/stages.h
deleted file mode 100644
index 671c02b3dd..0000000000
--- a/src/arch/armv7/include/arch/stages.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 The ChromiumOS Authors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __ARCH_STAGES_H
-#define __ARCH_STAGES_H
-
-extern void main(void);
-
-void stage_entry(void) __attribute__((section(".text.stage_entry.armv7")));
-void stage_exit(void *);
-
-#endif
diff --git a/src/arch/armv7/include/arch/types.h b/src/arch/armv7/include/arch/types.h
deleted file mode 100644
index be7e76c5ab..0000000000
--- a/src/arch/armv7/include/arch/types.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __ASM_ARM_TYPES_H
-#define __ASM_ARM_TYPES_H
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#define BITS_PER_LONG 32
-
-/* Dma addresses are 32-bits wide.  */
-
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-
-#endif
diff --git a/src/arch/armv7/include/armv7.h b/src/arch/armv7/include/armv7.h
deleted file mode 100644
index 147323457a..0000000000
--- a/src/arch/armv7/include/armv7.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef ARMV7_H
-#define ARMV7_H
-#include <types.h>
-
-/* Cortex-A9 revisions */
-#define MIDR_CORTEX_A9_R0P1	0x410FC091
-#define MIDR_CORTEX_A9_R1P2	0x411FC092
-#define MIDR_CORTEX_A9_R1P3	0x411FC093
-#define MIDR_CORTEX_A9_R2P10	0x412FC09A
-
-/* Cortex-A15 revisions */
-#define MIDR_CORTEX_A15_R0P0	0x410FC0F0
-
-/* CCSIDR */
-#define CCSIDR_LINE_SIZE_OFFSET		0
-#define CCSIDR_LINE_SIZE_MASK		0x7
-#define CCSIDR_ASSOCIATIVITY_OFFSET	3
-#define CCSIDR_ASSOCIATIVITY_MASK	(0x3FF << 3)
-#define CCSIDR_NUM_SETS_OFFSET		13
-#define CCSIDR_NUM_SETS_MASK		(0x7FFF << 13)
-
-/*
- * Values for InD field in CSSELR
- * Selects the type of cache
- */
-#define ARMV7_CSSELR_IND_DATA_UNIFIED	0
-#define ARMV7_CSSELR_IND_INSTRUCTION	1
-
-/* Values for Ctype fields in CLIDR */
-#define ARMV7_CLIDR_CTYPE_NO_CACHE		0
-#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY	1
-#define ARMV7_CLIDR_CTYPE_DATA_ONLY		2
-#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA	3
-#define ARMV7_CLIDR_CTYPE_UNIFIED		4
-
-/*
- * CP15 Barrier instructions
- * Please note that we have separate barrier instructions in ARMv7
- * However, we use the CP15 based instructions because we use
- * -march=armv5 in U-Boot
- */
-#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
-#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
-#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
-
-void v7_outer_cache_enable(void);
-void v7_outer_cache_disable(void);
-void v7_outer_cache_flush_all(void);
-void v7_outer_cache_inval_all(void);
-void v7_outer_cache_flush_range(u32 start, u32 end);
-void v7_outer_cache_inval_range(u32 start, u32 end);
-
-#endif
diff --git a/src/arch/armv7/include/assembler.h b/src/arch/armv7/include/assembler.h
deleted file mode 100644
index 10363c4e4e..0000000000
--- a/src/arch/armv7/include/assembler.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- *  arch/arm/include/asm/assembler.h
- *
- *  Copyright (C) 1996-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  This file contains arm architecture specific defines
- *  for the different processors.
- *
- *  Do not include any C declarations in this file - it is included by
- *  assembler source.
- */
-
-/*
- * Endian independent macros for shifting bytes within registers.
- */
-#ifndef __ARMEB__
-#define pull		lsr
-#define push		lsl
-#define get_byte_0	lsl #0
-#define get_byte_1	lsr #8
-#define get_byte_2	lsr #16
-#define get_byte_3	lsr #24
-#define put_byte_0	lsl #0
-#define put_byte_1	lsl #8
-#define put_byte_2	lsl #16
-#define put_byte_3	lsl #24
-#else
-#define pull		lsl
-#define push		lsr
-#define get_byte_0	lsr #24
-#define get_byte_1	lsr #16
-#define get_byte_2	lsr #8
-#define get_byte_3      lsl #0
-#define put_byte_0	lsl #24
-#define put_byte_1	lsl #16
-#define put_byte_2	lsl #8
-#define put_byte_3      lsl #0
-#endif
-
-/*
- * Data preload for architectures that support it
- */
-#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \
-	defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
-	defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \
-	defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \
-	defined(__ARM_ARCH_7R__)
-#define PLD(code...)	code
-#else
-#define PLD(code...)
-#endif
-
-/*
- * Cache aligned
- */
-#define CALGN(code...) code
-
-#define W(instr)	instr
diff --git a/src/arch/armv7/include/bootblock_common.h b/src/arch/armv7/include/bootblock_common.h
deleted file mode 100644
index 034a12bc36..0000000000
--- a/src/arch/armv7/include/bootblock_common.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#if CONFIG_CPU_HAS_BOOTBLOCK_INIT
-void bootblock_cpu_init(void);
-#else
-static void __attribute__((unused)) bootblock_cpu_init(void)
-{
-}
-#endif
-
-#if CONFIG_MAINBOARD_HAS_BOOTBLOCK_INIT
-void bootblock_mainboard_init(void);
-#else
-static void __attribute__((unused)) bootblock_mainboard_init(void)
-{
-}
-#endif
diff --git a/src/arch/armv7/include/clocks.h b/src/arch/armv7/include/clocks.h
deleted file mode 100644
index 58cf838621..0000000000
--- a/src/arch/armv7/include/clocks.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* Standard clock speeds */
-
-/*
- * We define some commonly-used clock speeds to avoid error since long
- * numbers are hard to read.
- *
- * The format of the label is
- * CLK_x_yU where:
- *	x is the integer speed
- *	y is the fractional part which can be omitted if 0
- *	U is the units (blank for Hz, K or M for KHz and MHz)
- *
- * Please order the items by increasing Hz
- */
-enum {
-	CLK_32768	= 32768,
-	CLK_20M		= 20000000,
-	CLK_24M		= 24000000,
-	CLK_144M	= 144000000,
-	CLK_216M	= 216000000,
-	CLK_300M	= 300000000,
-};
diff --git a/src/arch/armv7/include/smp/spinlock.h b/src/arch/armv7/include/smp/spinlock.h
deleted file mode 100644
index 1dc397c19c..0000000000
--- a/src/arch/armv7/include/smp/spinlock.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef ARCH_SMP_SPINLOCK_H
-#define ARCH_SMP_SPINLOCK_H
-
-/* FIXME: implement this for ARM */
-#error "implement this for ARM"
-#if 0
-/*
- * Your basic SMP spinlocks, allowing only a single CPU anywhere
- */
-
-typedef struct {
-	volatile unsigned int lock;
-} spinlock_t;
-
-
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
-#define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED;
-
-#define barrier() __asm__ __volatile__("": : :"memory")
-#define spin_is_locked(x)	(*(volatile char *)(&(x)->lock) != 0)
-#define spin_unlock_wait(x)	do { barrier(); } while(spin_is_locked(x))
-
-static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
-{
-	unsigned long tmp;
-	__asm__ __volatile__ (
-		"1:	ldrex	%0, [%1]\n"
-		"	teq	%0, #0\n"
-		"	strexeq	%0, %2, [%1]\n"
-		"	teqeq	%0, #0\n"
-		"	bne	1b\n"
-		: "=&r" (tmp)
-		: "r" (&lock->lock), "r" (1)
-		: "cc"
-	);
-	barrier();
-}
-
-static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock)
-{
-	__asm__ __volatile__(
-		"	str	%1, [%0]\n"
-		:
-		: "r" (&lock->lock), "r" (0)
-		: "cc"
-	);
-}
-
-#define cpu_relax() barrier()
-
-#endif
-#endif /* ARCH_SMP_SPINLOCK_H */
diff --git a/src/arch/armv7/include/stdint.h b/src/arch/armv7/include/stdint.h
deleted file mode 100644
index 9d41e6359a..0000000000
--- a/src/arch/armv7/include/stdint.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef ARM_STDINT_H
-#define ARM_STDINT_H
-
-#if defined(__GNUC__)
-#define __HAVE_LONG_LONG__ 1
-#else
-#define __HAVE_LONG_LONG__ 0
-#endif
-
-/* Exact integral types */
-typedef unsigned char      uint8_t;
-typedef signed char        int8_t;
-
-typedef unsigned short     uint16_t;
-typedef signed short       int16_t;
-
-typedef unsigned int       uint32_t;
-typedef signed int         int32_t;
-
-#if __HAVE_LONG_LONG__
-typedef unsigned long long uint64_t;
-typedef signed long long   int64_t;
-#endif
-
-/* Small types */
-typedef unsigned char      uint_least8_t;
-typedef signed char        int_least8_t;
-
-typedef unsigned short     uint_least16_t;
-typedef signed short       int_least16_t;
-
-typedef unsigned int       uint_least32_t;
-typedef signed int         int_least32_t;
-
-#if __HAVE_LONG_LONG__
-typedef unsigned long long uint_least64_t;
-typedef signed long long   int_least64_t;
-#endif
-
-/* Fast Types */
-typedef unsigned char      uint_fast8_t;
-typedef signed char        int_fast8_t;
-
-typedef unsigned int       uint_fast16_t;
-typedef signed int         int_fast16_t;
-
-typedef unsigned int       uint_fast32_t;
-typedef signed int         int_fast32_t;
-
-#if __HAVE_LONG_LONG__
-typedef unsigned long long uint_fast64_t;
-typedef signed long long   int_fast64_t;
-#endif
-
-/* Types for `void *' pointers.  */
-typedef int                intptr_t;
-typedef unsigned int       uintptr_t;
-
-/* Largest integral types */
-#if __HAVE_LONG_LONG__
-typedef long long int      intmax_t;
-typedef unsigned long long uintmax_t;
-#else
-typedef long int           intmax_t;
-typedef unsigned long int  uintmax_t;
-#endif
-
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-#if __HAVE_LONG_LONG__
-typedef uint64_t u64;
-#endif
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-
-#ifndef UINT32_MAX
-#define UINT32_MAX (4294967295U)
-#endif
-#ifndef UINT64_MAX
-# define UINT64_MAX (18446744073709551615ULL)
-#endif
-#ifndef UINT64_C
-#define UINT64_C(c) c ## ULL
-#endif
-#ifndef PRIu64
-#define PRIu64 "llu"
-#endif
-
-#undef __HAVE_LONG_LONG__
-
-#endif /* ARM_STDINT_H */
diff --git a/src/arch/armv7/include/utils.h b/src/arch/armv7/include/utils.h
deleted file mode 100644
index 828b86cb36..0000000000
--- a/src/arch/armv7/include/utils.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _UTILS_H_
-#define _UTILS_H_
-
-static inline s32 log_2_n_round_up(u32 n)
-{
-	s32 log2n = -1;
-	u32 temp = n;
-
-	while (temp) {
-		log2n++;
-		temp >>= 1;
-	}
-
-	if (n & (n - 1))
-		return log2n + 1; /* not power of 2 - round up */
-	else
-		return log2n; /* power of 2 */
-}
-
-static inline s32 log_2_n_round_down(u32 n)
-{
-	s32 log2n = -1;
-	u32 temp = n;
-
-	while (temp) {
-		log2n++;
-		temp >>= 1;
-	}
-
-	return log2n;
-}
-
-#endif