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-rw-r--r--payloads/libpayload/arch/x86/Kconfig3
-rw-r--r--payloads/libpayload/arch/x86/Makefile.inc2
-rw-r--r--payloads/libpayload/arch/x86/apic.c189
-rw-r--r--payloads/libpayload/arch/x86/exception.c11
-rw-r--r--payloads/libpayload/arch/x86/main.c7
-rw-r--r--payloads/libpayload/include/x86/arch/apic.h43
6 files changed, 255 insertions, 0 deletions
diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig
index 4a5e6bd88e..cbb21cbc14 100644
--- a/payloads/libpayload/arch/x86/Kconfig
+++ b/payloads/libpayload/arch/x86/Kconfig
@@ -34,4 +34,7 @@ config ARCH_SPECIFIC_OPTIONS # dummy
select LITTLE_ENDIAN
select IO_ADDRESS_SPACE
+config ENABLE_APIC
+ bool "Enables the Local APIC"
+
endif
diff --git a/payloads/libpayload/arch/x86/Makefile.inc b/payloads/libpayload/arch/x86/Makefile.inc
index 6517bf196c..268df1e542 100644
--- a/payloads/libpayload/arch/x86/Makefile.inc
+++ b/payloads/libpayload/arch/x86/Makefile.inc
@@ -45,3 +45,5 @@ libcbfs-$(CONFIG_LP_CBFS) += rom_media.c
# Multiboot support is configurable
libc-$(CONFIG_LP_MULTIBOOT) += multiboot.c
+
+libc-$(CONFIG_LP_ENABLE_APIC) += apic.c
diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c
new file mode 100644
index 0000000000..d5cf6ae14f
--- /dev/null
+++ b/payloads/libpayload/arch/x86/apic.c
@@ -0,0 +1,189 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright 2018 Google LLC.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload.h>
+#include <arch/apic.h>
+#include <arch/cpuid.h>
+#include <arch/msr.h>
+#include <exception.h>
+
+#define APIC_BASE_MSR 0x0000001B
+#define APIC_BASE_MASK (0xFFFFFFFULL << 12)
+
+#define CPUID_XAPIC_ENABLED_BIT (1 << 9)
+#define CPUID_XAPIC2_ENABLED_BIT (1 << 21)
+
+#define XAPIC_ENABLED_BIT (1 << 11)
+#define X2APIC_ENABLED_BIT (1 << 10)
+#define APIC_MASKED_BIT (1 << 16)
+#define APIC_SW_ENABLED_BIT (1 << 8)
+
+#define APIC_ID 0x020
+#define APIC_ID_SHIFT 24
+#define APIC_ID_MASK (0xFFUL << APIC_ID_SHIFT)
+#define APIC_VERSION 0x030
+#define APIC_MAX_LVT_SHIFT 16
+#define APIC_MAX_LVT_MASK (0xFFUL << APIC_MAX_LVT_SHIFT)
+#define APIC_TASK_PRIORITY 0x080
+#define APIC_TASK_PRIORITY_MASK 0xFFUL
+#define APIC_EOI 0x0B0
+#define APIC_SPURIOUS 0x0F0
+#define APIC_LVT_TIMER 0x320
+#define APIC_TIMER_INIT_COUNT 0x380
+#define APIC_TIMER_CUR_COUNT 0x390
+#define APIC_TIMER_DIV_CFG 0x3E0
+
+#define APIC_LVT_SIZE 0x010
+
+static uint32_t apic_bar;
+static int _apic_initialized;
+
+enum APIC_CAPABILITY {
+ DISABLED = 0,
+ XACPI = 1 << 0,
+ X2ACPI = 1 << 1
+};
+
+int apic_initialized(void)
+{
+ return _apic_initialized;
+}
+
+static inline uint32_t apic_read32(uint32_t offset)
+{
+ return read32((void *)(apic_bar + offset));
+}
+
+static inline void apic_write32(uint32_t offset, uint32_t value)
+{
+ write32((void *)(apic_bar + offset), value);
+}
+
+uint8_t apic_id(void)
+{
+ die_if(!apic_bar, "APIC is not initialized");
+
+ uint8_t id =
+ (apic_read32(APIC_ID) & APIC_ID_MASK) >> APIC_ID_SHIFT;
+
+ return id;
+}
+
+void apic_eoi(void)
+{
+ die_if(!apic_bar, "APIC is not initialized");
+
+ apic_write32(APIC_EOI, 0);
+}
+
+static enum APIC_CAPABILITY apic_capabilities(void)
+{
+ uint32_t eax, ebx, ecx, edx;
+
+ cpuid(1, eax, ebx, ecx, edx);
+
+ enum APIC_CAPABILITY capabilities = DISABLED;
+
+ if (edx & CPUID_XAPIC_ENABLED_BIT)
+ capabilities |= XACPI;
+
+ if (ecx & CPUID_XAPIC2_ENABLED_BIT)
+ capabilities |= X2ACPI;
+
+ return capabilities;
+}
+
+static uint8_t apic_max_lvt_entries(void)
+{
+ die_if(!apic_bar, "APIC is not initialized");
+
+ uint32_t reg = apic_read32(APIC_VERSION);
+ reg &= APIC_MAX_LVT_MASK;
+ reg >>= APIC_MAX_LVT_SHIFT;
+
+ return (uint8_t)reg;
+}
+
+static void apic_reset_all_lvts(void)
+{
+ uint8_t max = apic_max_lvt_entries();
+ for (int i = 0; i <= max; ++i) {
+ uint32_t offset = APIC_LVT_TIMER + APIC_LVT_SIZE * i;
+ apic_write32(offset, APIC_MASKED_BIT);
+ }
+}
+
+static void apic_set_task_priority(uint8_t priority)
+{
+ die_if(!apic_bar, "APIC is not initialized");
+
+ uint32_t tpr = apic_read32(APIC_TASK_PRIORITY);
+ tpr &= ~APIC_TASK_PRIORITY_MASK;
+ tpr |= priority;
+
+ apic_write32(APIC_TASK_PRIORITY, priority);
+}
+
+static void apic_sw_enable(void)
+{
+ uint32_t reg = apic_read32(APIC_SPURIOUS);
+ if (reg & APIC_SW_ENABLED_BIT)
+ return;
+
+ reg |= APIC_SW_ENABLED_BIT;
+
+ apic_write32(APIC_SPURIOUS, reg);
+}
+
+void apic_init(void)
+{
+ uint64_t apic_bar_reg;
+
+ printf("APIC Init Started\n");
+
+ die_if(apic_initialized(), "APIC already initialized");
+ die_if(!(apic_capabilities() & XACPI), "APIC is not supported");
+
+ apic_bar_reg = _rdmsr(APIC_BASE_MSR);
+
+ die_if(!(apic_bar_reg & XAPIC_ENABLED_BIT), "APIC is not enabled");
+ die_if(apic_bar_reg & X2APIC_ENABLED_BIT,
+ "APIC is configured in x2APIC mode which is not supported");
+
+ apic_bar = (uint32_t)(apic_bar_reg & APIC_BASE_MASK);
+
+ apic_reset_all_lvts();
+ apic_set_task_priority(0);
+
+ apic_sw_enable();
+
+ _apic_initialized = 1;
+
+ printf("APIC Configured\n");
+}
diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c
index d70d942a05..2691c85329 100644
--- a/payloads/libpayload/arch/x86/exception.c
+++ b/payloads/libpayload/arch/x86/exception.c
@@ -31,8 +31,16 @@
#include <exception.h>
#include <libpayload.h>
#include <stdint.h>
+#include <arch/apic.h>
#define IF_FLAG (1 << 9)
+/*
+ * Local and I/O APICs support 240 vectors (in the range of 16 to 255) as valid
+ * interrupts. The Intel 64 and IA-32 architectures reserve vectors 16
+ * through 31 for predefined interrupts, exceptions, and Intel-reserved
+ * encodings.
+*/
+#define FIRST_USER_DEFINED_VECTOR 32
u32 exception_stack[0x400] __attribute__((aligned(8)));
@@ -171,6 +179,9 @@ void exception_dispatch(void)
if (handlers[vec]) {
handlers[vec](vec);
+ if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)
+ && vec >= FIRST_USER_DEFINED_VECTOR)
+ apic_eoi();
return;
}
diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c
index f9a5e2cf83..05ffa0d83b 100644
--- a/payloads/libpayload/arch/x86/main.c
+++ b/payloads/libpayload/arch/x86/main.c
@@ -29,6 +29,7 @@
#include <exception.h>
#include <libpayload.h>
+#include <arch/apic.h>
unsigned long loader_eax; /**< The value of EAX passed from the loader */
unsigned long loader_ebx; /**< The value of EBX passed from the loader */
@@ -57,6 +58,12 @@ int start_main(void)
exception_init();
+ if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) {
+ apic_init();
+
+ enable_interrupts();
+ }
+
/*
* Any other system init that has to happen before the
* user gets control goes here.
diff --git a/payloads/libpayload/include/x86/arch/apic.h b/payloads/libpayload/include/x86/arch/apic.h
new file mode 100644
index 0000000000..fdd447361a
--- /dev/null
+++ b/payloads/libpayload/include/x86/arch/apic.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright 2018 Google LLC.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_INCLUDES_ARCH_APIC_H__
+#define __ARCH_X86_INCLUDES_ARCH_APIC_H__
+
+/** Returns 1 if apic_init has been called */
+int apic_initialized(void);
+
+void apic_init(void);
+
+uint8_t apic_id(void);
+
+/** Signal the end of the interrupt handler. */
+void apic_eoi(void);
+
+#endif /* __ARCH_X86_INCLUDES_ARCH_APIC_H__ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 05:06:31 +0000