1 files changed, 0 insertions, 90 deletions
diff --git a/payloads/libpayload/arch/arm64/lib/cache.c b/payloads/libpayload/arch/arm64/lib/cache.c
deleted file mode 100644
index 1de4012d4a..0000000000
--- a/payloads/libpayload/arch/arm64/lib/cache.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * cache.c: Cache Maintenance Instructions
- * Reference: ARM Architecture Reference Manual, ARMv8-A edition
- */
-
-#include <stdint.h>
-
-#include <arch/lib_helpers.h>
-
-void dccisw(uint64_t cisw)
-{
-	__asm__ __volatile__("dc cisw, %0\n\t" : : "r" (cisw) :"memory");
-}
-
-void dccivac(uint64_t civac)
-{
-	__asm__ __volatile__("dc civac, %0\n\t" : : "r" (civac) :"memory");
-}
-
-void dccsw(uint64_t csw)
-{
-	__asm__ __volatile__("dc csw, %0\n\t" : : "r" (csw) :"memory");
-}
-
-void dccvac(uint64_t cvac)
-{
-	__asm__ __volatile__("dc cvac, %0\n\t" : : "r" (cvac) :"memory");
-}
-
-void dccvau(uint64_t cvau)
-{
-	__asm__ __volatile__("dc cvau, %0\n\t" : : "r" (cvau) :"memory");
-}
-
-void dcisw(uint64_t isw)
-{
-	__asm__ __volatile__("dc isw, %0\n\t" : : "r" (isw) :"memory");
-}
-
-void dcivac(uint64_t ivac)
-{
-	__asm__ __volatile__("dc ivac, %0\n\t" : : "r" (ivac) :"memory");
-}
-
-void dczva(uint64_t zva)
-{
-	__asm__ __volatile__("dc zva, %0\n\t" : : "r" (zva) :"memory");
-}
-
-void iciallu(void)
-{
-	__asm__ __volatile__("ic iallu\n\t" : : :"memory");
-}
-
-void icialluis(void)
-{
-	__asm__ __volatile__("ic ialluis\n\t" : : :"memory");
-}
-
-void icivau(uint64_t ivau)
-{
-	__asm__ __volatile__("ic ivau, %0\n\t" : : "r" (ivau) :"memory");
-}