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Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/Intel/Board/board.html | 239 | ||||
| -rw-r--r-- | Documentation/Intel/Board/galileo.html | 113 | ||||
| -rw-r--r-- | Documentation/Intel/SoC/quark.html | 220 | ||||
| -rw-r--r-- | Documentation/Intel/SoC/soc.html | 730 | ||||
| -rw-r--r-- | Documentation/Intel/development.html | 377 | ||||
| -rw-r--r-- | Documentation/Intel/fsp1_1.html | 79 | ||||
| -rw-r--r-- | Documentation/Intel/index.html | 128 |
7 files changed, 0 insertions, 1886 deletions
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html deleted file mode 100644 index 0d4631ad51..0000000000 --- a/Documentation/Intel/Board/board.html +++ /dev/null @@ -1,239 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Board</title> - </head> - <body> - -<h1>x86 Board Development</h1> -<p> - Board development requires System-on-a-Chip (SoC) support. - The combined steps are listed - <a target="_blank" href="../development.html">here</a>. - The development steps for the board are listed below: -</p> -<ol> - <li><a href="#RequiredFiles">Required Files</a></li> - <li>Enable <a href="#SerialOutput">Serial Output</a></li> - <li>Load the <a href="#SpdData">Memory Timing Data</a></li> - <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li> - <li><a href="#AcpiTables">ACPI Tables</a></li> -</ol> - - -<hr> -<h2><a name="RequiredFiles">Required Files</a></h2> -<p> - Create the board directory as src/mainboard/<Vendor>/<Board>. -</p> - -<p> - The following files are required to build a new board: -</p> -<ol> - <li>Kconfig.name - Defines the Kconfig value for the board</li> - <li>Kconfig - <ol type="A"> - <li>Selects the SoC for the board and specifies the SPI flash size - <ol type="I"> - <li>BOARD_ROMSIZE_KB_<Size></li> - <li>SOC_<Vendor>_<Chip Family></li> - </ol> - </li> - <li>Declare the Kconfig values for: - <ol type="I"> - <li>MAINBOARD_DIR</li> - <li>MAINBOARD_PART_NUMBER</li> - <li>MAINBOARD_VENDOR</li> - </ol> - </li> - </ol> - </li> - <li>devicetree.cb - Enable root bridge and serial port - <ol type="A"> - <li>The first line must be "chip soc/Intel/<soc family>"; - this path is used by the generated static.c to include the chip.h - header file - </li> - </ol> - </li> - <li>romstage.c - <ol type="A"> - <li>Add routine mainboard_romstage_entry which calls romstage_common</li> - </ol> - </li> - <li>Configure coreboot build: - <ol type="A"> - <li>Set LOCALVERSION</li> - <li>Select vendor for the board</li> - <li>Select the board</li> - <li>CBFS_SIZE = 0x00100000</li> - <li>Set the CPU_MICROCODE_CBFS_LEN</li> - <li>Set the CPU_MICROCODE_CBFS_LOC</li> - <li>Set the FSP_IMAGE_ID_STRING</li> - <li>Set the FSP_LOC</li> - <li>No payload</li> - <li>Choose the default value for all other options</li> - </ol> - </li> -</ol> - - -<hr> -<h2><a name="SerialOutput">Enable Serial Output</a></h2> -<p> - Use the following steps to enable serial output: -</p> -<ol> - <li>Implement the car_mainboard_pre_console_init routine in the com_init.c - file: - <ol type="A"> - <li>Power on and enable the UART controller</li> - <li>Connect the UART receive and transmit data lines to the - appropriate SoC pins - </li> - </ol> - </li> - <li>Add Makefile.inc - <ol type="A"> - <li>Add com_init.c to romstage</li> - </ol> - </li> -</ol> - - -<hr> -<h2><a name="SpdData">Memory Timing Data</a></h2> -<p> - Memory timing data is located in the flash. This data is in the format of - <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a> - (SPD) data. - Use the following steps to load the SPD data: -</p> -<ol> - <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the - display of the SPD data being passed to MemoryInit - </li> - <li>Create an "spd" subdirectory</li> - <li>Create an spd/spd.c file for the SPD implementation - <ol type="A"> - <li>Implement the mainboard_fill_spd_data routine - <ol type="i"> - <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li> - <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li> - <li>Set the DIMM channel configuration</li> - </ol> - </li> - </ol> - </li> - <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li> - <li>Create spd/Makefile.inc - <ol type="A"> - <li>Add spd.c to romstage</li> - <li>Add the .spd.hex file to SPD_SOURCES</li> - </ol> - </li> - <li>Edit Makefile.inc to add the spd subdirectory</li> - <li>Edit romstage.c - <ol type="A"> - <li>Call mainboard_fill_spd_data</li> - <li>Add mainboard_memory_init_params to copy the SPD and DRAM - configuration data from the pei_data structure into the UPDs - for MemoryInit - </li> - </ol> - </li> - <li>Edit devicetree.cb - <ol type="A"> - <li>Include the UPD parameters for MemoryInit except for: - <ul> - <li>Address of SPD data</li> - <li>DRAM configuration set above</li> - </ul> - </li> - </ol> - </li> - <li>A working FSP - <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a> - routine is required to complete debugging</li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x34: - - Just after entering - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a> - </li> - <li>0x36: - - Just before displaying the - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a> - for FSP MemoryInit - </li> - <li>0x92: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a> - - Just before calling FSP - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a> - </li> - <li>0x37: - - Just after returning from FSP - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a> - </li> - </ol> - </li> - <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li> -</ol> - - - -<hr> -<h2><a name="DisablePciDevices">Disable PCI Devices</a></h2> -<p> - Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all - of the devices in the system. Edit the devicetree.cb file: -</p> -<ol> - <li>Edit the devicetree.cb file: - <ol type="A"> - <li>Add an entry for a PCI device.function and turn it off. The entry - should look similar to: -<pre><code>device pci 14.0 off end</code></pre> - </li> - <li>Turn on the devices for: - <ul> - <li>Memory Controller</li> - <li>Debug serial device</li> - </ul> - </li> - </ol> - </li> - <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li> -</ol> - - - -<hr> -<h2><a name="AcpiTables">ACPI Tables</a></h2> -<ol> - <li>Edit Kconfig - <ol type="A"> - <li>Add "select HAVE_ACPI_TABLES"</li> - </ol> - </li> - <li>Add the acpi_tables.c module: - <ol type="A"> - <li>Include soc/acpi.h</li> - <li>Add the acpi_create_fadt routine - <ol type="I"> - <li>fill in the ACPI header</li> - <li>Call the acpi_fill_fadt routine</li> - </ol> - </li> - </ol> - </li> - <li>Add the dsdt.asl module: - </li> -</ol> - - - -<hr> -<p>Modified: 20 February 2016</p> - </body> -</html> diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html deleted file mode 100644 index f7edf6e8ee..0000000000 --- a/Documentation/Intel/Board/galileo.html +++ /dev/null @@ -1,113 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Galileo</title> - </head> - <body> - -<h1>Intel® Galileo Development Board</h1> -<table> - <tr> - <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td> - <td> - The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® - <a target="_blank" href="../SoC/quark.html">Quark™</a> SoC: - <ul> - <li><a target="_blank" href="../development.html">Overall</a> development</li> - <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> - <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> - <li><a target="_blank" href="board.html">Board</a> support</li> - </ul> - </td> - </tr> -</table> - - - -<hr> -<h2>Galileo Board Documentation</h2> -<ul> - <li>Common Components - <ul> - <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> - <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> - <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li> - <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li> - <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb_1_35V_DDR3L.pdf">MT41K128M8</a></li> - <li>SoC: Intel® Quark™ <a target="_blank" href="../SoC/quark.html">X-1000</a></li> - <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> - <li>SPI Flash (8 MiB): Winbond™ <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li> - <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> - <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li> - <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li> - </ul> - </li> - <li>Make a bootable <a target="_blank" href="https://software.intel.com/en-us/get-started-galileo-linux-step1">micro SD card</a></li> -</ul> - -<h3>Galileo Gen 2 Board Documentation</h3> -<ul> - <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li> - <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li> - <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html">Overview</a></li> - <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li> - <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_330736_003.pdf">Product Brief</a></li> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g2-schematic.pdf">Schematic</a></li> - <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf">User Guide</a></li> - <li>Components - <ul> - <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> - <li>I2C 16-channel, 12-bit PWM: NXP Semiconductors <a target="_blank" href="http://cache.nxp.com/documents/data_sheet/PCA9685.pdf">PCA9685</a></li> - <li>I2C I/O Ports: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf">PCAL9535A</a></li> - <li>Octal Buffer/Driver: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv541at.pdf">SN74LV541AT</a></li> - <li>Quadruple Bus Buffer: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv125a.pdf">SN74LV125A</a></li> - <li>Quadruple Bus Buffer with 3-State Outputs: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf">SN74LVC126A</a></li> - <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> - <li>Single 2-input multiplexer: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/74LVC1G157.pdf">74LVC1G157</a></li> - <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> - </ul> - </li> -</ul> - -<h3>Galileo Gen 1 Board Documentation</h3> -<ul> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/galileo-g1-datasheet.pdf">Datasheet</a></li> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g1-schematic.pdf">Schematic</a></li> - <li>Components - <ul> - <li>A/D: Analog Devices <a target="_blank" href="http://www.analog.com/media/en/technical-documentation/data-sheets/AD7298-1.pdf">AD7298</a></li> - <li>Analog Switch, 2 channel: Texas Instruments <a target="_blank" href="http://www.ti.com.cn/cn/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> - <li>EEPROM & GPIO: Cypress <a target="_blank" href="http://www.cypress.com/file/37971/download">CY8C9540A</a></li> - <li>Power Distribution Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps2044b.pdf">TPS2051BDBVR</a></li> - <li>RS232 Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/max3232.pdf">MAX3232</a></li> - <li>Voltage-Level Translator: Texas Instruments<a target="_blank" href="http://www.ti.com/lit/ds/symlink/txs0108e.pdf">TXS0108E</a></li> - </ul> - </li> -</ul> - - - -<hr> -<h2>Debug Tools</h2> -<ul> - <li>Flash Programmer: - <ul> - <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li> - </ul> - </li> - <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-JTAG-20-10">Olimex ARM-JTAG-20-10</a></li> - <li>JTAG Debugger: - <ul> - <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-USB-OCD-H">ARM-USB-OCD-H</a></li> - <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li> - </ul> - </li> - <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopenocd_quark_appnote_330015_003.pdf">Hardware Setup and Software Installation</a></li> - <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=FTDI+TTL-232R-3V3">TTL-232R-3V3</a></li> -</ul> - - -<hr> -<p>Modified: 29 February 2016</p> - </body> -</html> diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html deleted file mode 100644 index c3eead2e33..0000000000 --- a/Documentation/Intel/SoC/quark.html +++ /dev/null @@ -1,220 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Quark™ SoC</title> - </head> - <body> - -<h1>Intel® Quark™ SoC</h1> -<table> - <tr> - <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png" width=500></a></td> - <td> - The Quark™ SoC code was developed using the - <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a> - board: - <ul> - <li><a target="_blank" href="../development.html">Overall</a> development</li> - <li><a target="_blank" href="soc.html">SoC</a> support</li> - <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> - <li><a target="_blank" href="../Board/board.html">Board</a> support</li> - <li><a target="_blank" href="#QuarkFsp">Quark™ FSP</a></li> - <li><a target="_blank" href="#CorebootPayloadPkg">CorebootPayloadPkg</a></li> - </ul> - </td> - </tr> -</table> - - - -<hr> -<h2>Quark™ Documentation</h2> -<ul> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png">Block Diagram</a></li> - <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specifications.html">Specifications</a>: - <ul> - <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a> - - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>: - <ul> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf">Datasheet</a></li> - <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/intelquarkcore_devman_001.pdf">Developer's Manual</a></li> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/intel-quark-product-brief-v3.pdf">Product Brief</a></li> - </ul> - </li> - </ul> - </li> - <li><a target="_blank" href="../index.html#Documentation">More documentation</a></li> -</ul> - - - -<hr> -<h2><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h2> -<p> -Build Instructions: -</p> -<ol> - <li>Set up <a href="#BuildEnvironment">build environment</a></li> - <li>Linux (assumes GCC48): -<pre><code>build -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -a IA32 \ - -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 \ - -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL \ - -DMAX_LOGICAL_PROCESSORS=1 -ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd -</code></pre> - </li> - <li>Windows (assumes Visual Studio 2015): -<pre><code>build -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -a IA32 -t VS2015x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL -DMAX_LOGICAL_PROCESSORS=1 -dir Build\CorebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd -</code></pre> - </li> - <li>In the .config for coreboot, set the following Kconfig values: - <ul> - <li>CONFIG_PAYLOAD_ELF=y</li> - <li>CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"</li> - </ul> - </li> - <li>Build coreboot</li> - <li>Copy the image build/coreboot.rom into flash</li> -</ol> - - - -<hr> -<h2><a name="BuildEnvironment">Quark™ EDK2 Build Environment</a></h2> -<p> - Use the following steps to setup a build environment: -</p> -<ol> - <li>Get the EDK2 sources: - <ol type="A"> - <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li> - <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li> - <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li> - </ol> - </li> - <li>Set up a build window: - <ul> - <li>Linux: -<pre><code>export WORKSPACE=$PWD -export PACKAGES_PATH="$PWD/edk2:$PWD/edk2-non-osi" -cd edk2 -export WORKSPACE=$PWD -. edksetup.sh -</code></pre> - </li> - <li>Windows: -<pre><code>set WORKSPACE=%CD% -set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\edk2-non-osi -set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 -cd edk2 -edksetup.bat -</code></pre> - </li> - </ul> - </li> -</ol> - - - -<hr> -<h2><a name="QuarkFsp">Quark™ FSP</a></h2> -<p> -Getting the Quark FSP source: -</p> -<ol> - <li>Set up an EDK-II <a href="#BuildEnvironment">Build Environment</a></li> - <li>cd edk2</li> - <li>mkdir QuarkFspPkg</li> - <li>cd QuarkFspPkg</li> - <li>Use git to clone <a target="_blank" href="https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp">QuarkFspPkg</a> into the QuarkFpsPkg directory (.)</li> -</ol> - -<h3>Building QuarkFspPkg</h3> -<p> -There are two versions of FSP: FSP 1.1 and FSP 2.0. There are also two -different implementations of FSP, one using subroutines without SEC and -PEI core and the original implementation which relies on SEC and PEI core. -Finally there are two different build x86 types release (r32) and debug (d32). -</p> -<p>Note that the subroutine implementations are a <b>work in progress</b>.</p> -<p> -Build commands shown building debug FSP: -</p> -<ul> - <li>Linux: - <ul> - <li>QuarkFspPkg/BuildFsp1_1.sh -d32</li> - <li>QuarkFspPkg/BuildFsp1_1Pei.sh -d32</li> - <li>QuarkFspPkg/BuildFsp2_0.sh -d32</li> - <li>QuarkFspPkg/BuildFsp2_0Pei.sh -d32</li> - </ul> - <li>Windows: - <ul> - <li>QuarkFspPkg/BuildFsp1_1.bat -d32</li> - <li>Windows: QuarkFspPkg/BuildFsp2_0.bat -d32</li> - </ul> - </li> -</ul> - -<h3>Copying FSP files into coreboot Source Tree</h3> -<p> -There are some helper scripts to copy the FSP output into the coreboot -source tree. The parameters to these scripts are: -</p> -<ol> - <li>EDK2 tree root</li> - <li>coreboot tree root</li> - <li>Build type: DEBUG or RELEASE</li> -</ol> -<p> -Script files: -</p> -<ul> - <li>Linux: - <ul> - <li>QuarkFspPkg/coreboot_fsp1_1.sh</li> - <li>QuarkFspPkg/coreboot_fsp1_1Pei.sh</li> - <li>QuarkFspPkg/coreboot_fsp2_0.sh</li> - <li>QuarkFspPkg/coreboot_fsp2_0Pei.sh</li> - </ul> -</ul> - - -<hr> -<h2>Quark™ EDK2 BIOS</h2> -<p> -Build Instructions: -</p> -<ol> - <li>Set up <a href="#BuildEnvironment">build environment</a></li> - <li>Build the image: - <ul> - <li>Linux: -<pre><code>build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -ls Build/Quark/DEBUG_GCC48/FV/Quark.fd -</code></pre> - </li> - <li>Windows: -<pre><code>build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -dir Build\Quark\DEBUG_VS2012x86\FV\Quark.fd -</code></pre> - </li> - </ul> - </li> -</ol> - -<p> -Documentation: -</p> -<ul> - <li><a target="_blank" href="https://github.com/tianocore/edk2/tree/master/QuarkPlatformPkg">EDK II firmware for Intel® Quark™ SoC X1000 based platforms</a></li> - <li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1000-uefi-firmware-writers-guide.pdf">UEFI Firmware Writer's Guide</a></li> -</ul> - - - -<hr> -<p>Modified: 17 May 2016</p> - </body> -</html> diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html deleted file mode 100644 index 8d565d52fe..0000000000 --- a/Documentation/Intel/SoC/soc.html +++ /dev/null @@ -1,730 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>SoC</title> - </head> - <body> - -<h1>x86 System on a Chip (SoC) Development</h1> -<p> - SoC development is best done in parallel with development for a specific - board. The combined steps are listed - <a target="_blank" href="../development.html">here</a>. - The development steps for the SoC are listed below: -</p> -<ol> - <li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> - <li>SoC <a href="#RequiredFiles">Required Files</a></li> - <li><a href="#Descriptor">Start Booting</a></li> - <li><a href="#EarlyDebug">Early Debug</a></li> - <li><a href="#Bootblock">Bootblock</a></li> - <li><a href="#TempRamInit">TempRamInit</a></li> - <li><a href="#Romstage">Romstage</a> - <ol type="A"> - <li>Enable <a href="#SerialOutput">Serial Output"</a></li> - <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li> - <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li> - <li>Disable the <a href="#DisableShadowRom">Shadow ROM</a></li> - </ol> - </li> - <li><a href="#Ramstage">Ramstage</a> - <ol type="A"> - <li><a href="#DeviceTree">Start Device Tree Processing</a></li> - <li>Set up the <a href="#MemoryMap">Memory Map"</a></li> - </ol> - </li> - <li><a href="#AcpiTables">ACPI Tables</a></li> - <li><a href="#LegacyHardware">Legacy Hardware</a></li> -</ol> - - -<hr> -<h2><a name="RequiredFiles">Required Files</a></h2> -<p> - Create the directory as src/soc/<Vendor>/<Chip Family>. -</p> - -<p> - The following files are required to build a new SoC: -</p> -<ul> - <li>Include files - <ul> - <li>include/soc/pei_data.h</li> - <li>include/soc/pm.h</li> - </ul> - </li> - <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool - chains for the various stages: - <ul> - <li>select ARCH_BOOTBLOCK_<Tool Chain></li> - <li>select ARCH_RAMSTAGE_<Tool Chain></li> - <li>select ARCH_ROMSTAGE_<Tool Chain></li> - <li>select ARCH_VERSTAGE_<Tool Chain></li> - </ul> - </li> - <li>Makefile.inc - Specify the include paths</li> - <li>memmap.c - Top of usable RAM</li> -</ul> - - -<hr> -<h2><a name="Descriptor">Start Booting</a></h2> -<p> - Some SoC parts require additional firmware components in the flash. - This section describes how to add those pieces. -</p> - -<h3>Intel Firmware Descriptor</h3> -<p> - The Intel Firmware Descriptor (IFD) is located at the base of the flash part. - The following command overwrites the base of the flash image with the Intel - Firmware Descriptor: -</p> -<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre> - - -<h3><a name="MEB">Management Engine Binary</a></h3> -<p> - Some SoC parts contain and require that the Management Engine (ME) be running - before it is possible to bring the x86 processor out of reset. A binary file - containing the management engine code must be added to the firmware using the - ifdtool. The following commands add this binary blob: -</p> -<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom -mv build/coreboot.rom.new build/coreboot.rom -</code></pre> - - -<h3><a name="EarlyDebug">Early Debug</a></h3> -<p> - Early debugging between the reset vector and the time the serial port is enabled - is most easily done by writing values to port 0x80. -</p> - - -<h3>Success</h3> -<p> - When the reset vector is successfully invoked, port 0x80 will output the following value: -</p> -<ul> - <li>0x01: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a> - - Bootblock successfully executed the - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a> - and entered the 16-bit code at - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a> - </li> -</ul> - - -<hr> -<h2><a name="Bootblock">Bootblock</a></h2> -<p> - Implement the bootblock using the following steps: -</p> -<ol> - <li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li> - <li>Add the timestamp.inc file which initializes the floating point registers and saves - the initial timestamp. - </li> - <li>Add the bootblock.c file which: - <ol type="A"> - <li>Enables memory-mapped PCI config access</li> - <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li> - <li>Enable ROM caching</li> - </ol> - </li> - <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file - <ol type="A"> - <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li> - <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li> - </ol> - </li> - <li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file - <ol type="A"> - <li>Add the bootblock subdirectory</li> - </ol> - </li> - <li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file - <ol type="A"> - <li>Add the fsp/memmap.h include file</li> - </ol> - </li> - <li>Add the necessary .h files to define the necessary values and structures</li> - <li>When successful port 0x80 will output the following values: - <ol type="A"> - <li>0x01: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a> - - Bootblock successfully executed the - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a> - and entered the 16-bit code at - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a> - </li> - <li>0x10: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a> - - Bootblock executing in - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a> - </li> - <li>0x10 - Verstage/romstage reached 32-bit mode</li> - </ol> - </li> -</ol> - -<p> - <b>Build Note:</b> The following files are included into the default bootblock image: -</p> -<ul> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a> - added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a> - and includes the following files: - <ul> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li> - <li>The code in - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a> - includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above - </li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li> - <li>The code in - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a> - invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc: - <ul> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li> - <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in - src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c - </li> - </ul> - </li> - </ul> - </li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a> - added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a> - </li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a> - added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a> - </li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a> - added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a> - </li> -</ul> - - -<hr> -<h2><a name="TempRamInit">TempRamInit</a></h2> -<p> - Enable the call to TempRamInit in two stages: -</p> -<ol> - <li>Finding the FSP binary in the read-only CBFS region</li> - <li>Call TempRamInit</li> -</ol> - - -<h3>Find FSP Binary</h3> -<p> -Use the following steps to locate the FSP binary: -</p> -<ol> - <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file - <ol type="A"> - <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a> - </li> - <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common - </li> - </ol> - </li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a> - - Just before calling - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a> - </li> - <li>Alternating 0xba and 0x01 - The FSP image was not found</li> - </ol> - </li> - <li>Add the <a target="_blank" href="../fsp1_1.html#FspBinary">FSP binary file</a> to the flash image</li> - <li>Set the following Kconfig values: - <ul> - <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li> - <li>CONFIG_FSP_IMAGE_ID_STRING</li> - </ul> - </li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a> - - Just before calling - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a> - </li> - <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li> - </ol> - </li> -</ol> - - -<h3>Calling TempRamInit</h3> -<p> -Use the following steps to debug the call to TempRamInit: -</p> -<ol> - <li>Add the CPU microcode update file - <ol type="A"> - <li>Add the microcode file with the following command -<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin</code></pre> - </li> - <li>Set the Kconfig values - <ul> - <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li> - <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li> - </ul> - </li> - </ol> - </li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a> - - Just before calling - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a> - </li> - <li>0x2A - Just before calling - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">cache_as_ram_main</a> - which is the start of the verstage code which may be part of romstage - </li> - </ol> - </li> -</ol> - - -<hr> -<h2><a name="Romstage">Romstage</a></h2> - -<h3><a name="SerialOutput">Serial Output</a></h3> -<p> - The following steps add the serial output support for romstage: -</p> -<ol> - <li>Create the romstage subdirectory</li> - <li>Add romstage/romstage.c - <ol type="A"> - <li>Program the necessary base addresses</li> - <li>Disable the TCO</li> - </ol> - </li> - <li>Add romstage/Makefile.inc - <ol type="A"> - <li>Add romstage.c to romstage</li> - </ol> - </li> - <li>Add gpio configuration support if necessary</li> - <li>Add the necessary .h files to support the build</li> - <li>Update Makefile.inc - <ol type="A"> - <li>Add the romstage subdirectory</li> - <li>Add the gpio configuration support file to romstage</li> - </ol> - </li> - <li>Set the necessary Kconfig values to enable serial output: - <ul> - <li>CONFIG_DRIVERS_UART_<driver>=y</li> - <li>CONFIG_CONSOLE_SERIAL=y</li> - <li>CONFIG_UART_FOR_CONSOLE=<port></li> - <li>CONFIG_CONSOLE_SERIAL_115200=y</li> - </ul> - </li> -</ol> - - -<h3><a name="PreviousSleepState">Determine Previous Sleep State</a></h3> -<p> - The following steps implement the code to get the previous sleep state: -</p> -<ol> - <li>Implement the fill_power_state routine which determines the previous sleep state</li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x32: - - Just after entering - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l99">romstage_common</a> - </li> - <li>0x33 - Just after calling - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l113">soc_pre_ram_init</a> - </li> - <li>0x34: - - Just after entering - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a> - </li> - </ol> -</ol> - - -<h3><a name="MemoryInit">MemoryInit Support</a></h3> -<p> - The following steps implement the code to support the FSP MemoryInit call: -</p> -<ol> - <li>Add the chip.h header file to define the UPD values which get passed - to MemoryInit. Skip the values containing SPD addresses and DRAM - configuration data which is determined by the board. - <p> - <b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb - file specifies the default values for these parameters. The build - process creates the static.c module which contains the config data - structure containing these values. - </p> - </li> - <li>Edit romstage/romstage.c - <ol type="A"> - <li>Implement the romstage/romstage.c/soc_memory_init_params routine to - copy the values from the config structure into the UPD structure - </li> - <li>Implement the soc_display_memory_init_params routine to display - the updated UPD parameters by calling fsp_display_upd_value - </li> - </ol> - </li> -</ol> - - -<h3><a name="DisableShadowRom">Disable Shadow ROM</a></h3> -<p> - A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff. - This shadow needs to be disabled to allow RAM to properly respond to - this address range. -</p> -<ol> - <li>Edit romstage/romstage.c and add the soc_after_ram_init routine</li> -</ol> - - -<hr> -<h2><a name="Ramstage">Ramstage</a></h2> - -<h3><a name="DeviceTree">Start Device Tree Processing</a></h3> -<p> - The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the - execution during ramstage. This file is processed by the util/sconfig utility - to generate build/mainboard/<Vendor>/<Board>/static.c. The various - state routines in - src/lib/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwaremain.c;hb=HEAD#l128">hardwaremain.c</a> - call dev_* routines which use the tables in static.c to locate operation tables - associated with the various chips and devices. After location the operation - tables, the state routines call one or more functions depending upon the - state of the state machine. -</p> - -<h4><a name="ChipOperations">Chip Operations</a></h4> -<p> - Kick-starting the ramstage state machine requires creating the operation table - for the chip listed in devicetree.cb: -</p> -<ol> - <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c: - <ol type="A"> - <li> - This chip's operation table has the name - soc_<SoC Vendor>_<SoC Family>_ops which is derived from the - chip path specified in the devicetree.cb file. - </li> - <li>Use the CHIP_NAME macro to specify the name for the chip</li> - <li>For FSP 1.1, specify a .init routine which calls intel_silicon_init</li> - </ol> - </li> - <li>Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage</li> -</ol> - -<h4>Domain Operations</h4> -<p> - coreboot uses the domain operation table to initiate operations on all of the - devices in the domain. By default coreboot enables all PCI devices which it - finds. Listing a device in devicetree.cb gives the board vendor control over - the device state. Non-PCI devices may also be listed under PCI device such as - the LPC bus or SMbus devices. -</p> -<ol> - <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c: - <ol type="A"> - <li> - The domain operation table is typically placed in - src/soc/<SoC Vendor>/<SoC Family>/chip.c. - The table typically looks like the following: -<pre><code>static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, -}; -</code></pre> - </li> - <li> - Create a .enable_dev entry in the chip operations table which points to a - routine which sets the domain table for the device with the DEVICE_PATH_DOMAIN. -<pre><code> if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } -</code></pre> - </li> - <li> - During the BS_DEV_ENUMERATE state, ramstage now display the device IDs - for the PCI devices on the bus. - </li> - </ol> - </li> - <li>Set CONFIG_DEBUG_BOOT_STATE=y in the .config file</li> - <li> - Debug the result until the PCI vendor and device IDs are displayed - during the BS_DEV_ENUMERATE state. - </li> -</ol> - - -<h3><a name="DeviceDrivers">PCI Device Drivers</a></h3> -<p> - PCI device drivers consist of a ".c" file which contains a "pci_driver" data - structure at the end of the file with the attribute tag "__pci_driver". This - attribute tag places an entry into a link time table listing the various - coreboot device drivers. -</p> -<p> - Specify the following fields in the table: -</p> -<ol> - <li>.vendor - PCI vendor ID value of the device</li> - <li>.device - PCI device ID value of the device or<br> - .devices - Address of a zero terminated array of PCI device IDs - </li> - <li>.ops - Operations table for the device. This is the address - of a "static struct device_operations" data structure specifying - the routines to execute during the different states and sub-states - of ramstage's processing. - </li> - <li>Turn on the device in mainboard/<Vendor>/<Board>/devicetree.cb</li> - <li> - Debug until the device is on and properly configured in coreboot and - usable by the payload - </li> -</ol> - -<h4><a name="SubsystemIds">Subsystem IDs</a></h4> -<p> - PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device - driver may use the common mechanism to assign subsystem IDs by adding - the ".ops_pci" to the pci_driver data structure. This field points to - a "struct pci_operations" that specifies a routine to set the subsystem - IDs for the device. The routine might look something like this: -</p> -<pre><code>static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - vendor = pci_read_config32(dev, PCI_VENDOR_ID); - device = vendor >> 16; - } - printk(BIOS_SPEW, - "PCI: %02x:%02x:%d subsystem vendor: 0x%04x, device: 0x%04x\n", - 0, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), - vendor & 0xffff, device); - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -</code></pre> - - - -<h3>Set up the <a name="MemoryMap">Memory Map</a></h3> -<p> - The memory map is built by the various PCI device drivers during the - BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically - specify the DRAM resources while the other drivers will typically specify - the IO resources. These resources are hung off the struct device *data structure by - src/device/device_util.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>. -</p> -<p> - During the BS_WRITE_TABLES state, coreboot collects these resources and - places them into a data structure identified by LB_MEM_TABLE. -</p> -<p> - Edit the device driver file: -</p> -<ol> - <li> - Implement a read_resources routine which calls macros defined in - src/include/device/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/device/device.h;hb=HEAD#l237">device.h</a> - like: - <ul> - <li>ram_resource</li> - <li>reserved_ram_resource</li> - <li>bad_ram_resource</li> - <li>uma_resource</li> - <li>mmio_resource</li> - </ul> - </li> -</ol> - -<p> - Testing: Verify that the resources are properly displayed by coreboot during the BS_WRITE_TABLES state. -</p> - - - -<hr> -<h2><a name="AcpiTables">ACPI Tables</a></h2> -<p> - One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. -</p> - -<h3>FADT</h3> -<p> - The EDK2 module - CorebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l450">CbParseLib.c</a> - requires that the FADT contains the values in the table below. - These values are placed into a HOB identified by - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootModulePkg.dec#l36">gUefiAcpiBoardInfoGuid</a> - by routine - CorebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPei/CbSupportPei.c#l364">CbPeiEntryPoint</a>. -</p> -<table border="1"> - <tr bgcolor="#c0ffc0"> - <td>coreboot Field</td> - <td>EDK2 Field</td> - <td>gUefiAcpiBoardInfoGuid</td> - <td>Use</li> - <td> - <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI Spec.</a> - Section - </td> - </tr> - <tr> - <td>gpe0_blk<br>gpe0_blk_len</td> - <td>Gpe0Blk<br>Gpe0BlkLen</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l477">PmGpeEnBase</a> - </td> - <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l129">Shutdown</a></td> - <td>4.8.4.1</td> - </tr> - <tr> - <td>pm1a_cnt_blk</td> - <td>Pm1aCntBlk</td> - <td>PmCtrlRegBase</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l139">Shutdown</a><br> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l40">Suspend</a> - </td> - <td>4.8.3.2.1</td> - </tr> - <tr> - <td>pm1a_evt_blk</td> - <td>Pm1aEvtBlk</td> - <td>PmEvtBase</td> - <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l134">Shutdown</a></td> - <td>4.8.3.1.1</td> - </tr> - <tr> - <td>pm_tmr_blk</td> - <td>PmTmrBlk</td> - <td>PmTimerRegBase</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c#l55">Timer</a> - </td> - <td>4.8.3.3</td> - </tr> - <tr> - <td>reset_reg.</td> - <td>ResetReg.Address</td> - <td>ResetRegAddress</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a> - and - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a> - resets - </td> - <td>4.3.3.6</td> - </tr> - <tr> - <td>reset_value</td> - <td>ResetValue</td> - <td>ResetValue</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a> - and - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a> - resets - </td> - <td>4.8.3.6</td> - </tr> -</table> -<p> - The EDK2 data structure is defined in - MdeModulePkg/Include/IndustryStandard/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandard/Acpi61.h#l111">Acpi61.h</a> - The coreboot data structure is defined in - src/arch/x86/include/arch/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/acpi/acpi.h;hb=HEAD#l237">acpi.h</a> -</p> - -<ol> - <li> - Select <a target="_blank" href="../Board/board.html#AcpiTables">HAVE_ACPI_TABLES</a> - in the board's Kconfig file - </li> - <li>Create a acpi.c module: - <ol type="A"> - <li>Add the acpi_fill_fadt routine and initialize the values above</li> - </ol> - </li> -</ol> - - - -<hr> -<h2><a name="LegacyHardware">Legacy Hardware</a></h2> -<p> - One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. -</p> - -<table border="1"> - <tr bgcolor="c0ffc0"> - <th>Peripheral</th> - <th>Use</th> - <th>8259 Interrupt Vector</th> - <th>IDT Base Offset</th> - <th>Interrupt Handler</th> - </tr> - <tr> - <td> - <a target="_blank" href="http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf">8254</a> - Programmable Interval Timer - </td> - <td> - EDK2: PcAtChipsetPkg/8254TimerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c">Timer.c</a> - </td> - <td>0</td> - <td>0x340</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c#l71">TimerInterruptHandler</a> - </td> - </tr> - <tr> - <td> - <a target="_blank" href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwibxYKU3ZDLAhVOzWMKHfuqB40QFggcMAA&url=http%3A%2F%2Fbochs.sourceforge.net%2Ftechspec%2Fintel-8259a-pic.pdf.gz&usg=AFQjCNF1NT0OQ6ys1Pn6Iv9sv6cKRzZbGg&sig2=HfBszp9xTVO_fajjPWCsJw">8259</a> - Programmable Interrupt Controller - </td> - <td> - EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c">8259.c</a> - </td> - <td> - Master interrupts: 0, 2 - 7<br> - Slave interrupts: 8 - 15<br> - Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15 - </td> - <td> - Master: 0x340, 0x350 - 0x378<br> - Slave: 0x380 - 0x3b8<br> - Interrupt descriptors are 8 bytes each - </td> - <td> </td> - </tr> -</table> - -<hr> -<p>Modified: 4 March 2016</p> - </body> -</html> diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html deleted file mode 100644 index 92b1d4be8d..0000000000 --- a/Documentation/Intel/development.html +++ /dev/null @@ -1,377 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Development</title> - </head> - <body> - -<h1>Intel® x86 coreboot/FSP Development Process</h1> -<p> - The x86 development process for coreboot is broken into the following components: -</p> -<ul> - <li>coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li> - <li>coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li> - <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li> -</ul> -<p> - The development process has two main phases: -</p> -<ol> - <li>Minimal coreboot; This phase is single threaded</li> - <li>Adding coreboot features</li> -</ol> - -<h2>Minimal coreboot</h2> -<p> - The combined steps below describe how to bring up a minimal coreboot for a - system-on-a-chip (SoC) and a development board: -</p> -<table> - <tr bgcolor="#ffffc0"> - <td>The initial coreboot steps are single threaded! - The initial minimal FSP development is also single threaded. - Progress can speed up by adding more developers after the minimal coreboot/FSP - implementation reaches the payload. - </td> - </tr> -</table> -<ol> - <li>Get the necessary tools: - <ul> - <li>Linux: Use your package manager to install m4 bison flex and the libcurses development - package. - <ul> - <li>Ubuntu or other Linux distribution that use apt, run: -<pre><code>sudo apt-get install m4 bison flex libncurses5-dev -</code></pre> - </li> - </ul> - </li> - </ul> - </li> - <li>Build the cross tools for i386: - <ul> - <li>Linux: -<pre><code>make crossgcc-i386</code></pre> - To use multiple processors for the toolchain build (which takes a long time), use: -<pre><code>make crossgcc-i386 CPUS=N</code></pre> - where N is the number of cores to use for the build. - </li> - </ul> - </li> - <li>Get something to build: - <ol type="A"> - <li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> - <li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li> - <li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li> - </ol> - </li> - <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> - <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> - <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> - <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> - <li>Enable the serial port - <ol type="A"> - <li>Power on, enable and configure GPIOs for the - <a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a> - </li> - <li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a> - support to romstage - </li> - </ol> - </li> - <li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li> - <li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li> - <li>Enable DRAM: - <ol type="A"> - <li>Implement the SoC - <a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a> - Support - </li> - <li>Implement the board support to read the - <a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a> - </li> - </ol> - </li> - <li>Disable the - <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a> - </li> - <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li> - <li> - Implement the .init routine for the - <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> - structure which calls FSP SiliconInit - </li> - <li> - Start ramstage's - <a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a> - to display the PCI vendor and device IDs - </li> - <li> - Disable the - <a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a> - </li> - <li> - Implement the - <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a> - </li> - <li>coreboot should now attempt to load the payload</li> -</ol> - - - -<h2>Add coreboot Features</h2> -<p> - Most of the coreboot development gets done in this phase. Implementation tasks in this - phase are easily done in parallel. -</p> -<ul> - <li>Payload and OS Features: - <ul> - <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li> - <li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li> - </ul> - </li> -</ul> - - - -<hr> -<table border="1"> - <tr bgcolor="#c0ffc0"> - <th colspan=3><h1>Features</h1></th> - </tr> - <tr bgcolor="#c0ffc0"> - <th>SoC</th> - <th>Where</th> - <th>Testing</th> - </tr> - <tr> - <td>8254 Programmable Interval Timer</td> - <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> - <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> - </tr> - <tr> - <td>8259 Programmable Interrupt Controller</td> - <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> - <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> - </tr> - <tr> - <td>Cache-as-RAM</td> - <td> - <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a> - FSP binary: - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br> - Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a> - called from - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br> - Disable: FSP 1.1 TempRamExit called from - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br> - </td> - <td>FindFSP: POST code 0x90 - (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>) - is displayed<br> - Enable: POST code - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a> - is displayed<br> - Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit - </td> - </tr> - <tr> - <td>Memory Map</td> - <td> - Implement a device driver for the - <a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a> - </td> - <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td> - </tr> - <tr> - <td>MTRRs</td> - <td> - Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/stack.c;hb=HEAD#l42">setup_stack_and_mtrrs</a><br> - Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l71">after_raminit.S</a> - </td> - <td>Set: Post code 0x91 - (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l213">POST_FSP_TEMP_RAM_EXIT</a>) - is displayed by - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br> - Load: Post code 0x3C is displayed by - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l152">after_raminit.S</a><br> - and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td> - </tr> - <tr> - <td>PCI Device Support</td> - <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td> - <td>The device is detected by coreboot and usable by the payload</td> - </tr> - <tr> - <td>Ramstage state machine</td> - <td> - Implement the chip and domain operations to start the - <a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a> - processing - </td> - <td> - During the BS_DEV_ENUMERATE state, ramstage now display the device IDs - for the PCI devices on the bus. - </td> - </tr> - <tr> - <td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td> - <td> - Disable: src/soc/<Vendor>/<Chip Family>/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a> - </td> - <td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td> - </tr> - - - <tr bgcolor="#c0ffc0"> - <th>Board</th> - <th>Where</th> - <th>Testing</th> - </tr> - <tr> - <td>Device Tree</td> - <td> - <a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting - the device tree processing<br> - <a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br> - Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a> - <td> - List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br> - Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br> - Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload - </td> - </tr> - <tr> - <td>DRAM</td> - <td> - Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br> - UPD Setup: - <ul> - <li>src/soc<Vendor>//<Chip Family>/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li> - <li>src/mainboard/<Vendor>/<Board>/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li> - </ul> - FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l126">raminit.c</a> - </td> - <td>Select the following Kconfig values - <ul> - <li>DISPLAY_HOBS</li> - <li>DISPLAY_UPD_DATA</li> - </ul> - Testing successful if: - <ul> - <li>MemoryInit UPD values are correct</li> - <li>MemoryInit returns 0 (success) and</li> - <li>The message "ERROR - coreboot's requirements not met by FSP binary!" - is not displayed - </li> - </ul> - </td> - </tr> - <tr> - <td>Serial Port</td> - <td> - SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br> - Enable: src/soc/mainboard/<Board>/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a> - </td> - <td>Debug serial output works</td> - </tr> - - - <tr bgcolor="#c0ffc0"> - <th>Payload</th> - <th>Where</th> - <th>Testing</th> - </tr> - <tr> - <td>ACPI Tables</td> - <td> - SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br> - </td> - <td>Verified by payload or OS</td> - </tr> - - - <tr bgcolor="#c0ffc0"> - <th>FSP</th> - <th>Where</th> - <th>Testing</th> - </tr> - <tr> - <td>TempRamInit</td> - <td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td> - <td>FSP binary found: POST code 0x90 - (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>) - is displayed<br> - TempRamInit successful: POST code - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a> - is displayed<br> - </td> - </tr> - <tr> - <td>MemoryInit</td> - <td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br> - <a target="_blank" href="Board/board.html#SpdData">Board</a> support<br> - </td> - <td>Select the following Kconfig values - <ul> - <li>DISPLAY_HOBS</li> - <li>DISPLAY_UPD_DATA</li> - </ul> - Testing successful if: - <ul> - <li>MemoryInit UPD values are correct</li> - <li>MemoryInit returns 0 (success) and</li> - <li>The message "ERROR - coreboot's requirements not met by FSP binary!" - is not displayed - </li> - </ul> - </td> - </tr> - <tr> - <td>TempRamExit</td> - <td>src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td> - <td>Post code 0x91 - (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>) - is displayed before calling TempRamExit by - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>, - CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and - Post code 0x39 is displayed by - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br> - </td> - </tr> - <tr> - <td>SiliconInit</td> - <td> - Implement the .init routine for the - <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure - </td> - <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td> - </tr> - <tr> - <td>FspNotify</td> - <td> - The code which calls FspNotify is located in - src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>. - The fsp_notify_boot_state_callback routine is called three times as specified - by the BOOT_STATE_INIT_ENTRY macros below the routine. - </td> - <td> - The FspNotify routines are called during: - <ul> - <li>BS_DEV_RESOURCES - on exit</li> - <li>BS_PAYLOAD_LOAD - on exit</li> - <li>BS_OS_RESUME - on entry (S3 resume)</li> - </ul> - </td> - </tr> -</table> - - - -<hr> -<p>Modified: 4 March 2016</p> - </body> -</html> diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html deleted file mode 100644 index 94cb6bf8be..0000000000 --- a/Documentation/Intel/fsp1_1.html +++ /dev/null @@ -1,79 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>FSP 1.1</title> - </head> - <body> - -<h1>FSP 1.1</h1> - -<h2>x86 FSP 1.1 Integration</h2> -<p> - Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC) - and board support. The combined steps are listed - <a target="_blank" href="development.html">here</a>. - The development steps for FSP are listed below: -</p> -<ol> - <li><a href="#RequiredFiles">Required Files</a></li> - <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li> - <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li> -</ol> - -<p> - FSP Documentation: -</p> -<ul> - <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> -</ul> - -<hr> -<h2><a name="RequiredFiles">Required Files</a></h2> -<h3><a name="corebootRequiredFiles">coreboot Required Files</a></h3> -<ol> - <li>Create the following directories if they do not already exist: - <ul> - <li>src/vendorcode/intel/fsp/fsp1_1/<Chip Family></li> - <li>3rdparty/blobs/mainboard/<Board Vendor>/<Board Name></li> - </ul> - </li> - <li> - The following files may need to be copied from the FSP build or release into the - directories above if they are not present or are out of date: - <ul> - <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h</li> - <li>FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin</li> - </ul> - </li> -</ol> - - -<hr> -<h2><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h2> -<p> - Add the FSP binary to the coreboot flash image using the following command: -</p> -<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre> -<p> - This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the - FSP code for TempRamInit may be executed in place. -</p> - - -<hr> -<h2><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h2> -<p> - Set the following Kconfig values: -</p> -<ul> - <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li> - <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li> - <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li> - <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li> -</ul> - - -<hr> -<p>Modified: 17 May 2016</p> - </body> -</html> diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html deleted file mode 100644 index 9d8aad05e9..0000000000 --- a/Documentation/Intel/index.html +++ /dev/null @@ -1,128 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Intel® x86</title> - </head> - <body> - -<h1>Intel® x86</h1> - -<h2>Intel® x86 Boards</h2> -<ul> - <li><a target="_blank" href="Board/galileo.html">Galileo</a></li> - <li><a target="_blank" href="http://wiki.minnowboard.org/Coreboot">MinnowBoard MAX</a></li> -</ul> - -<h2>Intel® x86 SoCs</h2> -<ul> - <li><a target="_blank" href="SoC/quark.html">Quark™</a></li> -</ul> - - - -<hr> -<h2>x86 coreboot Development</h2> -<ul> - <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> - <li><a target="_blank" href="development.html">Overall</a> development</li> - <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration - </li> - <li><a target="_blank" href="SoC/soc.html">SoC</a> support</li> - <li><a target="_blank" href="Board/board.html">Board</a> support</li> -</ul> - - - -<hr> -<h2>Payload Development</h2> -<ul> - <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> - <ul> - <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process">EDK II Development Process</a></li> - <li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20papers">White Papers</a></li> - <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github-Quick-Start">SourceForge to Github Quick Start</a></li> - <li>UEFI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_A.PDF">2.5 Errata A</a></li> - </ul> - </li> -</ul> - - - -<hr> -<h2><a name="Documentation">Documentation</a></h2> -<ul> - <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li> - <li><a target="_blank" href="http://www.uefi.org/specifications">UEFI Specifications</a></li> -</ul> - -<h3><a name="Edk2Documentation">EDK-II Documentation</a></h3> -<ul> - <li>Build <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/Build_Spec_1_26.pdf">V1.26</a></li> - <li>Coding Standards <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf">V2.1</a></li> - <li>DEC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DEC_Spec_1_25.pdf">V1.25</a></li> - <li>DSC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DSC_Spec_1_26.pdf">V1.26</a></li> - <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/UEFI-Driver-Writer's-Guide">Driver Writer's Guide</a></li> - <li>Expression Syntax <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/ExpressionSyntax_1.1.pdf">V1.1</a></li> - <li>FDF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/FDF_Spec_1_26.pdf">V1.26</a></li> - <li>INF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/INF_Spec_1_25.pdf">V1.25</a></li> - <li>PCD <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/PCD_Infrastructure.pdf">PCD</a>V0.55</li> - <li>UNI <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/UNI_File_Spec_v1_2_Errata_A.pdf">V1.2 Errata A</a></li> - <li>VRF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/VFR_1_9.pdf">V1.9</a></li> -</ul> - -<h3><a name="FspDocumentation">FSP Documentation</a></h3> -<ul> - <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf">V2.0</a></li> - <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> - <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf">V1.0</a></li> -</ul> - -<h3><a name="FeatureDocumentation">Feature Documentation</a></h3> -<table border="1"> - <tr bgcolor="#c0ffc0"><th>Feature/Specification</th><th>Linux View/Test</th><th>EDK-II View/Test</th></tr> - <tr> - <td><a target="_blank" href="https://en.wikipedia.org/wiki/E820">e820</a></td> - <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/dmesg.1.html">dmesg</a></td> - <td> </td> - </tr> - <tr> - <td><a target="_blank" href="http://www.uefi.org/specifications">ACPI</a></td> - <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/precise/man1/acpidump.1.html">acpidump</a></td> - <td> </td> - </tr> - <tr> - <td><a target="_blank" href="https://en.wikipedia.org/wiki/Extended_Display_Identification_Data">EDID</a></td> - <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/get-edid.1.html">get-edid | parse-edid</a></td> - <td> </td> - </tr> - <tr> - <td><a target="_blank" href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I2C</a></td> - <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/get-edid.1.html">i2cdetect</a></td> - <td> </td> - </tr> - <tr> - <td><a target="_blank" href="http://www.intel.com/design/archives/processors/pro/docs/242016.htm">Multiprocessor</a></td> - <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/lscpu.1.html">lscpu</a></td> - <td> </td> - </tr> - <tr> - <td><a target="_blank" href="https://pcisig.com/specifications">PCI</a></td> - <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man8/lspci.8.html">lspci</a></td> - <td><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI_Shell_Spec_2_0.pdf">pci</a></td> - </tr> - <tr> - <td><a target="_blank" href="https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf">SMBIOS</a></td> - <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man8/dmidecode.8.html">dmidecode</a></td> - <td><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI_Shell_Spec_2_0.pdf">smbiosview</a></td> - </tr> - <tr> - <td><a target="_blank" href="http://www.usb.org/developers/docs/">USB</a></td> - <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/xenial/man8/lsusb.8.html">lsusb</a></td> - <td> </td> - </tr> -</table> - -<hr> -<p>Modified: 18 June 2016</p> - </body> -</html> |