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Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/mainboard/emulation/spike-riscv.md | 23 | ||||
| -rw-r--r-- | Documentation/mainboard/index.md | 6 |
2 files changed, 29 insertions, 0 deletions
diff --git a/Documentation/mainboard/emulation/spike-riscv.md b/Documentation/mainboard/emulation/spike-riscv.md new file mode 100644 index 0000000000..55e87d9cc9 --- /dev/null +++ b/Documentation/mainboard/emulation/spike-riscv.md @@ -0,0 +1,23 @@ +# Spike RISC-V emulator + +[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator. + + +## Installation + +- Download `riscv-fesvr` and `riscv-isa-sim` from <https://github.com/riscv/> +- Apply the two patches in <https://github.com/riscv/riscv-isa-sim/pull/53>, + which are necessary in order to have a serial console +- Compile `riscv-fesvr` and then `riscv-isa-sim` + + +## Building coreboot and running it in Spike + +- Configure coreboot and run `make` as usual +- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to + convert coreboot to an ELF that Spike can load +- Run `spike -m1024 build/coreboot.elf` + + +[Spike]: https://github.com/riscv/riscv-isa-sim +[RISC-V]: https://riscv.org/ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c346a3b8f0..c1e5262a98 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -10,6 +10,12 @@ This section contains documentation about coreboot on specific mainboards. - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +## Emulation + +The boards in this section are not real mainboards, but emulators. + +- [Spike RISC-V emulator](emulation/spike-riscv.md) + ## Foxconn - [D41S](foxconn/d41s.md) |