diff options
Diffstat (limited to 'Documentation/util')
| -rw-r--r-- | Documentation/util/abuild/index.md | 14 | ||||
| -rw-r--r-- | Documentation/util/intelp2m/index.md | 18 |
2 files changed, 16 insertions, 16 deletions
diff --git a/Documentation/util/abuild/index.md b/Documentation/util/abuild/index.md index 4def2f6a49..31a267e1e5 100644 --- a/Documentation/util/abuild/index.md +++ b/Documentation/util/abuild/index.md @@ -14,7 +14,7 @@ to make sure your patch compiles cleanly for all. Note that abuild is a tool to do a simple build test, and binaries it produces may well not boot if flashed to a system. -### Basic usage +## Basic usage abuild needs to be run from the coreboot directory. If you cd into the coreboot/util/abuild directory and try to run it from there, it will @@ -30,7 +30,7 @@ example, to build the Lenovo X230 target, run: $ util/abuild/abuild -t lenovo/x230 ``` -### Where builds and logs are stored +## Where builds and logs are stored The resulting images and logs are stored in directory coreboot-builds/ under your current directory. This can be overridden with --outdir: @@ -53,7 +53,7 @@ coreboot-builds/passing_boards and coreboot-builds/failing_boards. **These logs are overwritten with each abuild run.** Save them elsewhere if you feel a need to reference the results later. -### Payloads +## Payloads You can also specify a payload directory with -p: @@ -81,7 +81,7 @@ You can also tell abuild not to use a payload: util/abuild/abuild -t lenovo/x230 -p none ``` -### Build non-default configurations +## Build non-default configurations Sometimes you do need to build test a custom, non-default configuration. This can be accomplished by placing a config file in configs/. @@ -142,7 +142,7 @@ a file named `myconfig` with this line: and run `abuild -K myconfig` to build everything with a silent postcar stage. -### Selectively build certain targets only (also config file naming caveats) +## Selectively build certain targets only (also config file naming caveats) The P8Z77-M PRO example above would fail for P8Z77-M, because the config file name is ambiguous. `abuild` would pick up this config when @@ -166,7 +166,7 @@ util/abuild/abuild --skip_unset USE_NATIVE_RAMINIT This example skips building configs not using (Sandy/Ivy Bridge) native RAM init. -### Additional Examples +## Additional Examples Many boards have multiple variants. You can build for a specific variant of a board: @@ -203,7 +203,7 @@ Of course, the real power of abuild is in testing multiple boards. util/abuild/abuild -B -y -c 8 -p none ``` -### Full options list +## Full options list ```text coreboot autobuild v0.11.01 (Feb 3, 2023) diff --git a/Documentation/util/intelp2m/index.md b/Documentation/util/intelp2m/index.md index 6873c1b1ea..98b9c009d6 100644 --- a/Documentation/util/intelp2m/index.md +++ b/Documentation/util/intelp2m/index.md @@ -11,7 +11,7 @@ make ./intelp2m -file /path/to/inteltool.log ``` -### Platforms +## Platforms It is possible to use templates for parsing inteltool.log files. To specify such a pattern, use the option `-t <template number>`. @@ -51,13 +51,13 @@ platform type is set using the -p option (Sunrise by default): ./intelp2m -p <platform> -file path/to/inteltool.log ``` -### Packages +## Packages ![][pckgs] [pckgs]: gopackages.png -### Bit fields in macros +## Bit fields in macros Use the `-fld=cb` option to only generate a sequence of bit fields in a new macro: @@ -71,7 +71,7 @@ _PAD_CFG_STRUCT(GPIO_37, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_TRIG(OFF), \ PAD_PULL(DN_20K)), /* LPSS_UART0_TXD */ ``` -### Raw DW0, DW1 register value +## Raw DW0, DW1 register value To generate the gpio.c with raw PAD_CFG_DW0 and PAD_CFG_DW1 register values you need to use the -fld=raw option: @@ -96,7 +96,7 @@ _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000), _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000), ``` -### Macro Check +## Macro Check After generating the macro, the utility checks all used fields of the configuration registers. If some field has been @@ -115,7 +115,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), ``` -### Information level +## Information level The utility can generate additional information about the bit fields of the DW0 and DW1 configuration registers. Using the @@ -158,7 +158,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, \ DISPUPD), ``` -### Ignoring Fields +## Ignoring Fields Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields from it that are not in the corresponding PAD_CFG_*() macro: @@ -177,7 +177,7 @@ _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), \ PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), ``` -### FSP-style macro +## FSP-style macro The utility allows one to generate macros that include fsp/edk2-platform style bitfields: @@ -205,6 +205,6 @@ style bitfields: GpioPadConfigLock }, ``` -### Supported Chipsets +## Supported Chipsets Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonLake-LP SoCs |