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Diffstat (limited to 'Documentation/soc')
| -rw-r--r-- | Documentation/soc/intel/icelake/iceLake_coreboot_development.md | 67 | ||||
| -rw-r--r-- | Documentation/soc/intel/icelake/index.md | 7 | ||||
| -rw-r--r-- | Documentation/soc/intel/index.md | 1 |
3 files changed, 0 insertions, 75 deletions
diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md deleted file mode 100644 index 214733140b..0000000000 --- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md +++ /dev/null @@ -1,67 +0,0 @@ -# Intel Ice Lake coreboot development - -## Introduction - -This document captures the coreboot development strategy for Intel SoC named Ice lake. - -The Ice Lake processor family is the next generation Intel® Core processor family. -These processors are built using Intel's 10 nm+ process. - -* [What is Ice Lake?](https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html) - -## Development Strategy - -Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model". - -1. Intel develops initial Firmware code for Ice Lake SoC. - -2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC. - ```eval_rst - :doc:`../../../mainboard/intel/icelake_rvp` - ``` - -### Summary: -* SoC is Ice Lake. -* Reference platform is icelake_rvp. -* OEM board is Dragonegg. - -## Create coreboot Image - -1. Clone latest coreboot code as below - ```bash - $ git clone https://review.coreboot.org/coreboot.git - ``` - -2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations - - Note: - Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site. - After product launch, FSP binary will be available externally as any other program. - -3. Create coreboot .config - -4. Build toolchain - ```bash - CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl - ``` - -5. Build image - ```bash - $ make # the image is generated as build/coreboot.rom - ``` - -## Flashing coreboot - -Flashing mechanism might be different between Intel RVP (Reference Validation Platform) and Chromebooks: - -* Make use of dediprog while flashing coreboot image on Intel-RVP -* For Chromebook related platform like dragonegg, one can flash via servo: - -```bash - $ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on - $ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image> - $ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off -``` -### References -* [flashrom](https://flashrom.org/Flashrom) -* [Servo](https://www.chromium.org/chromium-os/servo) diff --git a/Documentation/soc/intel/icelake/index.md b/Documentation/soc/intel/icelake/index.md deleted file mode 100644 index 71397d21bf..0000000000 --- a/Documentation/soc/intel/icelake/index.md +++ /dev/null @@ -1,7 +0,0 @@ -# Intel Ice Lake SOC-specific documentation - -This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs. - -## Ice Lake coreboot development - -- [Ice Lake coreboot development](iceLake_coreboot_development.md) diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 8da9cacc6e..b10b28885b 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -7,7 +7,6 @@ This section contains documentation about coreboot on specific Intel SOCs. - [Common code development strategy](code_development_model/code_development_model.md) - [FSP](fsp/index.md) - [Broadwell](broadwell/index.md) -- [Ice Lake/9th Gen Core-i series](icelake/index.md) - [MP Initialization](mp_init/mp_init.md) - [Microcode Updates](microcode.md) - [Firmware Interface Table](fit.md) |