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Diffstat (limited to 'Documentation/soc/intel/broadwell/blobs.md')
| -rw-r--r-- | Documentation/soc/intel/broadwell/blobs.md | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/soc/intel/broadwell/blobs.md b/Documentation/soc/intel/broadwell/blobs.md index b9f99afe66..01ce7c9827 100644 --- a/Documentation/soc/intel/broadwell/blobs.md +++ b/Documentation/soc/intel/broadwell/blobs.md @@ -29,6 +29,25 @@ field. For boards with an Intel GbE device, a modification of `refcode` is neede otherwise `refcode` will disable the Intel GbE device and the OS cannot find it in the list of PCI devices. +For the refcode binary extracted from Purism Librem 13 v1 (SHA256: +8a919ffece61ba21664b1028b0ebbfabcd727d90c1ae2f72b48152b8774323a4, +.program section starts at file offset 0x2040), we can see the +following code sequence: + + 1e06b: c6 43 0c 00 movb $0x0,0xc(%ebx) + 1e06f: c6 83 7e 03 00 00 00 movb $0x0,0x37e(%ebx) + 1e076: c6 83 70 03 00 00 01 movb $0x1,0x370(%ebx) + 1e07d: 66 89 43 0a mov %ax,0xa(%ebx) + 1e081: c6 83 da 01 00 00 01 movb $0x1,0x1da(%ebx) + 1e088: c6 83 86 03 00 00 01 movb $0x1,0x386(%ebx) + +The code at 0x1e06f sets the field that is to enable the GbE to the +hardcoded 0 value. Change the byte at 0x1e075 (file offset 0x200b5) +to 0x01 to make the refcode support Intel GbE: + + cp refcode.elf refcode_gbe.elf + printf '\x01' | dd of=refcode_gbe.elf bs=1 seek=131253 count=1 conv=notrunc + ## Use Broadwell SoC code for Haswell ULT boards Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT |