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-rw-r--r--Documentation/Intel/NativeRaminit/SandyBridge_registers.md2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md
index 2dce11bcc8..c96189088c 100644
--- a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md
+++ b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md
@@ -966,7 +966,7 @@ Please handle with care !
*Width:* 24 Bit
-*Desc:* TC_DBP - Timming of DDR - Bin Parameter Register, Channel 0
+*Desc:* TC_DBP - Timing of DDR - Bin Parameter Register, Channel 0
|Bit| Description |
|---|-------------|