diff options
Diffstat (limited to 'Documentation/Intel/NativeRaminit/Sandybridge_freq.md')
| -rw-r--r-- | Documentation/Intel/NativeRaminit/Sandybridge_freq.md | 63 |
1 files changed, 48 insertions, 15 deletions
diff --git a/Documentation/Intel/NativeRaminit/Sandybridge_freq.md b/Documentation/Intel/NativeRaminit/Sandybridge_freq.md index 50c6362c81..cf68d5ec46 100644 --- a/Documentation/Intel/NativeRaminit/Sandybridge_freq.md +++ b/Documentation/Intel/NativeRaminit/Sandybridge_freq.md @@ -4,16 +4,25 @@ This chapter explains the frequency selection done on Sandybride and Ivybridge. ## Definitions +```eval_rst ++---------+-------------------------------------------------------------------+------------+--------------+ | Symbol | Description | Units | Valid region | -|---------|-------------------------------------------------------------------|------------|--------------| -| SCK | DRAM system clock cycle time | s | - | -| tCK | DRAM system clock cycle time | 1/256th ns | - | -| DCK | Data clock cycle time: The time between two SCK clock edges | s | - | -| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - | -| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 | -| MULT | DRAM PLL multiplier | - | [3-12] | -| XMP | Extreme Memory Profiles | - | - | - ++=========+===================================================================+============+==============+ +| SCK | DRAM system clock cycle time | s | | ++---------+-------------------------------------------------------------------+------------+--------------+ +| tCK | DRAM system clock cycle time | 1/256th ns | | ++---------+-------------------------------------------------------------------+------------+--------------+ +| DCK | Data clock cycle time: The time between two SCK clock edges | s | | ++---------+-------------------------------------------------------------------+------------+--------------+ +| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | | ++---------+-------------------------------------------------------------------+------------+--------------+ +| REFCK | Reference clock, either 100 or 133 | MHz | 100, 133 | ++---------+-------------------------------------------------------------------+------------+--------------+ +| MULT | DRAM PLL multiplier | | [3-12] | ++---------+-------------------------------------------------------------------+------------+--------------+ +| XMP | Extreme Memory Profiles | | | ++---------+-------------------------------------------------------------------+------------+--------------+ +``` ## SPD The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect") located on every DIMM is factory program with various timings. One of them @@ -84,31 +93,54 @@ multiplier to select the DRAM frequency (SCK) by the following formula: > **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK. ## Sandy Bride's supported frequencies +```eval_rst ++------------+-----------+------------------+-------------------------+---------------+ | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment | -|------------|-----------|------------------|-------------------------|---------------| ++============+===========+==================+=========================+===============+ | 400 | DDR3-800 | 3 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 533 | DDR3-1066 | 4 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 666 | DDR3-1333 | 5 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 800 | DDR3-1600 | 6 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 933 | DDR3-1866 | 7 | 133 MHz | | -| 1066 | DDR3-2166 | 8 | 133 MHz | || ++------------+-----------+------------------+-------------------------+---------------+ +| 1066 | DDR3-2166 | 8 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ +``` ## Ivybridge's supported frequencies +```eval_rst ++------------+-----------+------------------+-------------------------+---------------+ | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment | -|------------|-----------|------------------|-------------------------|---------------| ++============+===========+==================+=========================+===============+ | 400 | DDR3-800 | 3 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 533 | DDR3-1066 | 4 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 666 | DDR3-1333 | 5 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 800 | DDR3-1600 | 6 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 933 | DDR3-1866 | 7 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 1066 | DDR3-2166 | 8 | 133 MHz | | ++------------+-----------+------------------+-------------------------+---------------+ | 700 | DDR3-1400 | 7 | 100 MHz | '1 | ++------------+-----------+------------------+-------------------------+---------------+ | 800 | DDR3-1600 | 8 | 100 MHz | '1 | ++------------+-----------+------------------+-------------------------+---------------+ | 900 | DDR3-1800 | 9 | 100 MHz | '1 | ++------------+-----------+------------------+-------------------------+---------------+ | 1000 | DDR3-2000 | 10 | 100 MHz | '1 | ++------------+-----------+------------------+-------------------------+---------------+ | 1100 | DDR3-2200 | 11 | 100 MHz | '1 | -| 1200 | DDR3-2400 | 12 | 100 MHz | '1 || - ++------------+-----------+------------------+-------------------------+---------------+ +| 1200 | DDR3-2400 | 12 | 100 MHz | '1 | ++------------+-----------+------------------+-------------------------+---------------+ +``` > '1: since coreboot 4.6 ## Multiplier selection @@ -120,7 +152,8 @@ else: freq_max := soft_fuse_max_mhz for i in SPDs: - freq_max := MIN(freq_max, ddr_spd_max_mhz[i])``` + freq_max := MIN(freq_max, ddr_spd_max_mhz[i]) +``` As you can see, by using DIMMs with different maximum DRAM frequencies, the slowest DIMMs' frequency will be selected, to prevent over-clocking it. |