diff options
| -rw-r--r-- | src/soc/mediatek/mt8186/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/mcucfg.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/pll.c | 20 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/soc.c | 2 |
4 files changed, 15 insertions, 11 deletions
diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 7a61bbf793..2107ab83e2 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c @@ -31,6 +32,7 @@ romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8186/include/soc/mcucfg.h b/src/soc/mediatek/mt8186/include/soc/mcucfg.h index 2418406962..48ca33dd51 100644 --- a/src/soc/mediatek/mt8186/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8186/include/soc/mcucfg.h @@ -942,6 +942,6 @@ check_member(mt8186_mcucfg_regs, mcusys_reserved_reg1_rd, 0x7ff4); check_member(mt8186_mcucfg_regs, mcusys_reserved_reg2_rd, 0x7ff8); check_member(mt8186_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc); -static struct mt8186_mcucfg_regs *const mt8186_mcucfg = (void *)MCUCFG_BASE; +static struct mt8186_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE; #endif /* SOC_MEDIATEK_MT8186_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c index 8201a5afff..7f9d74890c 100644 --- a/src/soc/mediatek/mt8186/pll.c +++ b/src/soc/mediatek/mt8186/pll.c @@ -425,13 +425,13 @@ void mt_pll_init(void) setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL1_EN); setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL2_EN); - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); write32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, 0x805f0603); write32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, 0xb07f0603); @@ -450,7 +450,7 @@ void mt_pll_init(void) void mt_pll_raise_little_cpu_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable armpll_ll frequency output */ clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8186_PLL_EN); @@ -463,13 +463,13 @@ void mt_pll_raise_little_cpu_freq(u32 freq) udelay(PLL_EN_DELAY); /* switch clock source back to armpll_ll */ - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } void mt_pll_raise_cci_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable ccipll frequency output */ clrbits32(plls[APMIXED_CCIPLL].reg, MT8186_PLL_EN); @@ -482,7 +482,7 @@ void mt_pll_raise_cci_freq(u32 freq) udelay(PLL_EN_DELAY); /* switch clock source back to ccipll */ - clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c index 360893ceee..dcb9703e07 100644 --- a/src/soc/mediatek/mt8186/soc.c +++ b/src/soc/mediatek/mt8186/soc.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <soc/emi.h> +#include <soc/mmu_operations.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -11,6 +12,7 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); } static struct device_operations soc_ops = { |