diff options
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 3 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index c72698f3d6..26ed64e0f1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -365,6 +365,12 @@ struct soc_intel_tigerlake_config { /* External Vnn Voltage in mV */ int vnn_sx_voltage_mv; } ext_fivr_settings; + + /* + * Enable(1)/Disable(0) CPU Replacement check. + * Default 0. Setting this to 1 to check CPU replacement. + */ + uint8_t CpuReplacementCheck; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 1a46b7a86d..1f60b52656 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -199,6 +199,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Command Pins Mirrored */ m_cfg->CmdMirror[0] = config->CmdMirror; + + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |