diff options
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 3 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 00470a201a..ae9f09e51e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -332,6 +332,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->IshEnable = cfg->integrated_sensor_hub_enable; + silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; + /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index aabd42df42..fa79cf83b9 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -101,6 +101,9 @@ struct soc_intel_apollolake_config { uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ + + /* Configure LPSS S0ix Enable */ + uint8_t lpss_s0ix_enable; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ |