diff options
| -rw-r--r-- | src/mainboard/google/veyron_pinky/romstage.c | 18 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/bootblock.c | 11 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/memlayout.ld | 3 |
3 files changed, 17 insertions, 15 deletions
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 1d7812b3e0..6f9b9d1392 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -64,10 +64,6 @@ void main(void) uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); #endif - /* used for MMU and CBMEM setup, in MB */ - u32 dram_start_mb = (uintptr_t)_dram/MiB; - u32 dram_size_mb = CONFIG_DRAM_SIZE_MB; - u32 dram_end_mb = dram_start_mb + dram_size_mb; console_init(); @@ -80,18 +76,12 @@ void main(void) #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); #endif - mmu_init(); - /* Device memory below DRAM is uncached. */ - mmu_config_range(0, dram_start_mb, DCACHE_OFF); - /* DRAM is cached. */ - mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); - /* A window for DMA is uncached. */ + + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ + mmu_config_range((uintptr_t)_dram/MiB, + CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); - /* The space above DRAM is uncached. */ - if (dram_end_mb < 4096) - mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); - dcache_mmu_enable(); cbmem_initialize_empty(); diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index eec3456613..b2f5bd9553 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -17,10 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/cache.h> #include <arch/io.h> #include <bootblock_common.h> #include <console/console.h> #include <soc/rockchip/rk3288/grf.h> +#include <symbols.h> #include "addressmap.h" #include "timer.h" #include "clock.h" @@ -41,4 +43,13 @@ static void bootblock_cpu_init(void) } rkclk_init(); + + mmu_init(); + /* Start with a clean slate. */ + mmu_config_range(0, 4096, DCACHE_OFF); + /* SRAM is tightly wedged between registers, need to use subtables. Map + * write-through as equivalent for non-cacheable without XN on A17. */ + mmu_config_range_kb((uintptr_t)_sram/KiB, + _sram_size/KiB, DCACHE_WRITETHROUGH); + dcache_mmu_enable(); } diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld index 6faec63ba5..2ddb6a6077 100644 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -34,7 +34,8 @@ SECTIONS SRAM_START(0xFF700000) TTB(0xFF700000, 16K) - BOOTBLOCK(0xFF704004, 16K - 4) + BOOTBLOCK(0xFF704004, 15K - 4) + TTB_SUBTABLES(0xFF707c00, 1K) VBOOT2_WORK(0xFF708000, 16K) OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K) PRERAM_CBFS_CACHE(0xFF716000, 4K) |