diff options
-rw-r--r-- | src/mainboard/protectli/vault_cml/Kconfig | 2 | ||||
-rw-r--r-- | src/mainboard/protectli/vault_cml/acpi/superio.asl | 13 | ||||
-rw-r--r-- | src/mainboard/protectli/vault_cml/bootblock.c | 8 | ||||
-rw-r--r-- | src/mainboard/protectli/vault_cml/devicetree.cb | 20 | ||||
-rw-r--r-- | src/mainboard/protectli/vault_cml/dsdt.asl | 5 |
5 files changed, 30 insertions, 18 deletions
diff --git a/src/mainboard/protectli/vault_cml/Kconfig b/src/mainboard/protectli/vault_cml/Kconfig index 6e7136d6f2..fa6606343d 100644 --- a/src/mainboard/protectli/vault_cml/Kconfig +++ b/src/mainboard/protectli/vault_cml/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_COMETLAKE_2 if BOARD_PROTECTLI_VP4630_VP4650 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPI_FLASH_MACRONIX - select SUPERIO_ITE_IT8786E + select SUPERIO_ITE_IT8784E config MAINBOARD_DIR default "protectli/vault_cml" diff --git a/src/mainboard/protectli/vault_cml/acpi/superio.asl b/src/mainboard/protectli/vault_cml/acpi/superio.asl index 853b0877b3..f5c9191a3e 100644 --- a/src/mainboard/protectli/vault_cml/acpi/superio.asl +++ b/src/mainboard/protectli/vault_cml/acpi/superio.asl @@ -1 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8784E_SHOW_UARTA +#undef IT8784E_SHOW_UARTB +#undef IT8784E_SHOW_EC +#undef IT8784E_SHOW_KBC +#undef IT8784E_SHOW_PS2M +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8784E_SHOW_SP1 +#define IT8784E_SHOW_EC +#include <superio/ite/it8784e/acpi/superio.asl> diff --git a/src/mainboard/protectli/vault_cml/bootblock.c b/src/mainboard/protectli/vault_cml/bootblock.c index 9052fb8631..82c46f985f 100644 --- a/src/mainboard/protectli/vault_cml/bootblock.c +++ b/src/mainboard/protectli/vault_cml/bootblock.c @@ -3,18 +3,18 @@ #include <bootblock_common.h> #include <soc/gpio.h> #include <superio/ite/common/ite.h> -#include <superio/ite/it8786e/it8786e.h> +#include <superio/ite/it8784e/it8784e.h> #include "gpio.h" -#define UART_DEV PNP_DEV(0x2e, IT8786E_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8786E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8784E_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8784E_GPIO) void bootblock_mainboard_early_init(void) { /* CLKIN freq 24MHz, Ext CLKIN for Watchdog, Internal VCC_OK */ ite_reg_write(GPIO_DEV, 0x23, 0x49); /* Set pin native functions */ - ite_reg_write(GPIO_DEV, 0x26, 0x00); + ite_reg_write(GPIO_DEV, 0x26, 0xf3); /* Set GPIOS exposed on pin header as GPIO functions */ ite_reg_write(GPIO_DEV, 0x29, 0xc0); /* External CLKIN PCICLK */ diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 154d81a4a9..3ba2b0198d 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -192,17 +192,17 @@ chip soc/intel/cannonlake device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on - chip superio/ite/it8786e - register "TMPIN1.mode" = "THERMAL_PECI" - register "TMPIN1.offset" = "0x63" + chip superio/ite/it8784e + register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_MODE_DISABLED" - register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" + register "TMPIN3.mode" = "THERMAL_PECI" + register "TMPIN3.offset" = "0x63" register "ec.vin_mask" = "VIN_ALL" register "ec.smbus_24mhz" = "1" register "ec.smbus_en" = "1" # FAN1 is CPU fan (connector on board) register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = " 1" + register "FAN1.smart.tmpin" = " 3" register "FAN1.smart.tmp_off" = "40" register "FAN1.smart.tmp_start" = "60" register "FAN1.smart.tmp_full" = "85" @@ -215,24 +215,18 @@ chip soc/intel/cannonlake io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on # COM 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end + device pnp 2e.2 on end # COM 2 device pnp 2e.3 off end # Printer Port device pnp 2e.4 on # Environment Controller io 0x60 = 0xa40 io 0x62 = 0xa30 irq 0x70 = 9 + irq 0xf0 = 0x80 # clear 3VSB status end device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # Mouse device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # COM 3 - device pnp 2e.9 off end # COM 4 device pnp 2e.a off end # CIR - device pnp 2e.b off end # COM 5 - device pnp 2e.c off end # COM 6 end chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/protectli/vault_cml/dsdt.asl b/src/mainboard/protectli/vault_cml/dsdt.asl index cb0922a5ea..8240fc9415 100644 --- a/src/mainboard/protectli/vault_cml/dsdt.asl +++ b/src/mainboard/protectli/vault_cml/dsdt.asl @@ -21,5 +21,10 @@ DefinitionBlock( #include <soc/intel/cannonlake/acpi/southbridge.asl> } + Scope (\_SB.PCI0.LPCB) + { + #include "acpi/superio.asl" + } + #include <southbridge/intel/common/acpi/sleepstates.asl> } |