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-rw-r--r--src/acpi/chromeos-gnvs.c6
-rw-r--r--src/mainboard/google/link/acpi_tables.c7
-rw-r--r--src/mainboard/google/slippy/acpi_tables.c7
-rw-r--r--src/soc/amd/picasso/acpi.c6
-rw-r--r--src/soc/amd/stoneyridge/acpi.c6
-rw-r--r--src/soc/intel/alderlake/acpi.c11
-rw-r--r--src/soc/intel/apollolake/acpi.c6
-rw-r--r--src/soc/intel/baytrail/acpi.c14
-rw-r--r--src/soc/intel/braswell/acpi.c13
-rw-r--r--src/soc/intel/broadwell/pch/lpc.c13
-rw-r--r--src/soc/intel/cannonlake/acpi.c13
-rw-r--r--src/soc/intel/elkhartlake/acpi.c11
-rw-r--r--src/soc/intel/icelake/acpi.c12
-rw-r--r--src/soc/intel/jasperlake/acpi.c11
-rw-r--r--src/soc/intel/skylake/acpi.c13
-rw-r--r--src/soc/intel/tigerlake/acpi.c11
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c10
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c6
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c11
19 files changed, 16 insertions, 171 deletions
diff --git a/src/acpi/chromeos-gnvs.c b/src/acpi/chromeos-gnvs.c
index bdd7d69cc5..b1588fa93c 100644
--- a/src/acpi/chromeos-gnvs.c
+++ b/src/acpi/chromeos-gnvs.c
@@ -4,12 +4,6 @@
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
-/* Remove once implemented on platform code. */
-__weak void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
-{
- return NULL;
-}
-
void gnvs_assign_chromeos(void)
{
chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
index f37f37e6cf..5b0621efc1 100644
--- a/src/mainboard/google/link/acpi_tables.c
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -2,8 +2,6 @@
#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-#include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/gnvs.h>
#include "thermal.h"
void acpi_create_gnvs(struct global_nvs *gnvs)
@@ -16,11 +14,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
-#if CONFIG(CHROMEOS)
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
-#endif
-
gnvs->tmps = CTDP_SENSOR_ID;
gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF;
diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c
index 666143cbe1..fcafd88988 100644
--- a/src/mainboard/google/slippy/acpi_tables.c
+++ b/src/mainboard/google/slippy/acpi_tables.c
@@ -3,8 +3,6 @@
#include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <device/device.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-#include <ec/google/chromeec/ec.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/nvs.h>
@@ -23,11 +21,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
-#if CONFIG(CHROMEOS)
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
-#endif
-
gnvs->tmps = TEMPERATURE_SENSOR_ID;
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 4b40e9be9e..743b32ca4f 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -396,12 +396,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
void acpi_create_gnvs(struct global_nvs *gnvs)
{
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&gnvs->chromeos);
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
-
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
gnvs->gpei = ~0ULL;
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index aadf3a2938..dd8f29f15f 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -164,12 +164,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
void acpi_create_gnvs(struct global_nvs *gnvs)
{
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&gnvs->chromeos);
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
-
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
gnvs->gpei = ~0ULL;
diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c
index 4ebe0d5102..616f29e620 100644
--- a/src/soc/intel/alderlake/acpi.c
+++ b/src/soc/intel/alderlake/acpi.c
@@ -9,7 +9,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci_ops.h>
-#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@@ -289,16 +288,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
-
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 0a9b16e909..92d1daf3c4 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -77,12 +77,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
struct soc_intel_apollolake_config *cfg;
cfg = config_of_soc();
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&gnvs->chromeos);
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
-
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 72326e76a0..35b26d3abf 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -21,9 +21,6 @@
#include <soc/pattrs.h>
#include <soc/pm.h>
-#include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-
#define MWAIT_RES(state, sub_state) \
{ \
.addrl = (((state) << 4) | (sub_state)), \
@@ -69,17 +66,6 @@ void acpi_init_gnvs(struct global_nvs *gnvs)
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
-
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else {
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
- }
}
int acpi_sci_irq(void)
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 82aff9351d..bdba5830a6 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -11,7 +11,6 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>
#include <device/pci.h>
-#include <ec/google/chromeec/ec.h>
#include <drivers/intel/gma/opregion.h>
#include <soc/acpi.h>
#include <soc/gfx.h>
@@ -24,7 +23,6 @@
#include <soc/pm.h>
#include <string.h>
#include <types.h>
-#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
#define MWAIT_RES(state, sub_state) \
@@ -72,17 +70,6 @@ void acpi_init_gnvs(struct global_nvs *gnvs)
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
-
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else {
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
- }
}
int acpi_sci_irq(void)
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 4d4d8610f2..8feae0f0a1 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -13,8 +13,6 @@
#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
-#include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/gnvs.h>
#include <string.h>
#include <soc/gpio.h>
#include <soc/iobp.h>
@@ -618,17 +616,6 @@ static void southcluster_inject_dsdt(const struct device *device)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else {
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
- }
-
/* Add it to DSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32) gnvs);
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 1d4419b583..0a09cd4746 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -8,7 +8,6 @@
#include <console/console.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
-#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@@ -20,7 +19,6 @@
#include <soc/pm.h>
#include <soc/systemagent.h>
#include <string.h>
-#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
#include "chip.h"
@@ -194,17 +192,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else {
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
- }
-
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c
index 6d76b66cbe..f0c0c74f4e 100644
--- a/src/soc/intel/elkhartlake/acpi.c
+++ b/src/soc/intel/elkhartlake/acpi.c
@@ -9,7 +9,6 @@
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
-#include <ec/google/chromeec/ec.h>
#include <intelblocks/acpi.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
@@ -257,16 +256,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
-
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index 30917f304b..565dc65e90 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -6,7 +6,6 @@
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
#include <cbmem.h>
-#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@@ -18,7 +17,6 @@
#include <soc/soc_chip.h>
#include <soc/systemagent.h>
#include <string.h>
-#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
/*
@@ -189,16 +187,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
-
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
index 1591953dcc..8494911996 100644
--- a/src/soc/intel/jasperlake/acpi.c
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -9,7 +9,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <device/pci_ops.h>
-#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@@ -284,16 +283,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
-
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index a045f2d61c..0f3136e4c4 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -12,7 +12,6 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/common/common.h>
#include <cpu/intel/turbo.h>
-#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/sgx.h>
@@ -30,7 +29,6 @@
#include <soc/systemagent.h>
#include <string.h>
#include <types.h>
-#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
#include <device/pci_ops.h>
@@ -168,17 +166,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else {
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
- }
-
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index f21953dd84..7f15a96707 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -9,7 +9,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci_ops.h>
-#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@@ -284,16 +283,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
-
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 0a99d80620..a37d298d06 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -647,6 +647,11 @@ size_t gnvs_size_of_array(void)
return sizeof(struct global_nvs);
}
+void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
+{
+ return &gnvs->chromeos;
+}
+
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs = acpi_get_gnvs();
@@ -659,11 +664,6 @@ void southbridge_inject_dsdt(const struct device *dev)
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
-#if CONFIG(CHROMEOS)
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
-#endif
-
-
/* Add it to DSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32) gnvs);
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index c4712baf66..39cae48d10 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -458,6 +458,12 @@ size_t gnvs_size_of_array(void)
return sizeof(struct global_nvs);
}
+/* To build emulation/qemu-q35 with CHROMEOS. */
+void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
+{
+ return 0;
+}
+
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs = acpi_get_gnvs();
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 1f768c2603..ae718c16a5 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -690,6 +690,11 @@ uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs)
return &gnvs->cbmc;
}
+void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
+{
+ return &gnvs->chromeos;
+}
+
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs;
@@ -703,12 +708,6 @@ void southbridge_inject_dsdt(const struct device *dev)
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
-#if CONFIG(CHROMEOS)
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
-#endif
-
-
-
/* Add it to DSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32)gnvs);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 17:13:40 +0000