diff options
| -rw-r--r-- | src/cpu/intel/model_f2x/Config.lb | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_f2x/model_f2x_init.c | 4 | ||||
| -rw-r--r-- | src/cpu/intel/socket_mPGA604_533Mhz/chip.h | 2 | ||||
| -rw-r--r-- | src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c | 2 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2735/Config.lb | 370 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2735/auto.c | 37 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2735/chip.h | 2 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2735/failover.c | 16 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2735/mainboard.c | 4 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2735/mptable.c | 26 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4880/Options.lb | 2 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/Options.lb | 2 | ||||
| -rw-r--r-- | targets/tyan/s2735/Config.lb | 272 | ||||
| -rw-r--r-- | targets/tyan/s2735/ns2735 | 2 |
14 files changed, 243 insertions, 500 deletions
diff --git a/src/cpu/intel/model_f2x/Config.lb b/src/cpu/intel/model_f2x/Config.lb index 76544328e6..508e1da172 100644 --- a/src/cpu/intel/model_f2x/Config.lb +++ b/src/cpu/intel/model_f2x/Config.lb @@ -7,4 +7,4 @@ dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/intel/microcode dir /cpu/intel/hyperthreading -driver model_f1x_init.o +driver model_f2x_init.o diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index db8dc184e3..4f69d81d2a 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -30,7 +30,7 @@ static uint32_t microcode_updates[] = { }; -static void model_f2x_init(device_t dev) +static void model_f2x_init(device_t cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -48,7 +48,7 @@ static void model_f2x_init(device_t dev) }; static struct device_operations cpu_dev_ops = { - .init = model_f1x_init, + .init = model_f2x_init, }; static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0f22 }, diff --git a/src/cpu/intel/socket_mPGA604_533Mhz/chip.h b/src/cpu/intel/socket_mPGA604_533Mhz/chip.h index f08d8eef50..bf5cbc70eb 100644 --- a/src/cpu/intel/socket_mPGA604_533Mhz/chip.h +++ b/src/cpu/intel/socket_mPGA604_533Mhz/chip.h @@ -1,4 +1,4 @@ -extern struct chip_operations cpu_intel_socket_mPGA604_533Mhz_control; +extern struct chip_operations cpu_intel_socket_mPGA604_533Mhz_ops; struct cpu_intel_socket_mPGA604_533Mhz_config { }; diff --git a/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c b/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c index aba9cd3ec4..0831ac09c0 100644 --- a/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c +++ b/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c @@ -2,6 +2,6 @@ #include "chip.h" -struct chip_operations cpu_intel_socket_mPGA604_533Mhz_control = { +struct chip_operations cpu_intel_socket_mPGA604_533Mhz_ops = { .name = "socket mPGA604_533Mhz", }; diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb index a5de70ba1b..eb1bb5c934 100644 --- a/src/mainboard/tyan/s2735/Config.lb +++ b/src/mainboard/tyan/s2735/Config.lb @@ -1,230 +1,200 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses ARCH -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION -# -# -### -### Set all of the defaults for an x86 architecture -### -# -# -### -### Build the objects we have code for in this directory. -### -##object mainboard.o -config chip.h -register "fixup_scsi" = "1" -register "fixup_vga" = "1" +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +arch i386 end ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Build the objects we have code for in this directory. ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 driver mainboard.o -#dir /drvers/adaptec/7902 -#dir /drivers/si/3114 -#dir /drivers/intel/82551_ipmi -#dir /drivers/ati/ragexl if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -# -#default HARD_RESET_BUS=1 -#default HARD_RESET_DEVICE=4 -#default HARD_RESET_FUNCTION=0 -# -arch i386 end -# -### -### Build our 16 bit and 32 bit linuxBIOS entry code -### -mainboardinit cpu/i386/entry16.inc -mainboardinit cpu/i386/entry32.inc -mainboardinit cpu/i386/bist32.inc -ldscript /cpu/i386/entry16.lds -ldscript /cpu/i386/entry32.lds -# -### -### Build our reset vector (This is where linuxBIOS is entered) -### -if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds -else - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds -end -# -#### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc -# -### -### Include an id string (For safe flashing) -### -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -# -#### -#### This is the early phase of linuxBIOS startup -#### Things are delicate and we test to see if we should -#### failover to another image. -#### -#option MAX_REBOOT_CNT=2 -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end -# -### -### Setup our mtrrs -### -#mainboardinit cpu/p6/earlymtrr.inc -### -### Only the bootstrap cpu makes it here. -### Failover if we need to -### -# -if USE_FALLBACK_IMAGE - mainboardinit ./failover.inc -end - -# -# -### -### Setup the serial port -### -mainboardinit pc80/serial.inc -mainboardinit arch/i386/lib/console.inc -mainboardinit cpu/i386/bist32_fail.inc -# -#### -#### O.k. We aren't just an intermediary anymore! -#### -# -### -### When debugging disable the watchdog timer -### -##option MAXIMUM_CONSOLE_LOGLEVEL=7 -#default MAXIMUM_CONSOLE_LOGLEVEL=7 -# -#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end -# -### -### Romcc output -### +#object reset.o +## +## Romcc output +## makerule ./failover.E depends "$(MAINBOARD)/failover.c" action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" end makerule ./failover.inc - depends "./romcc ./failover.E" + depends "./failover.E ./romcc" action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h" - action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" + depends "$(MAINBOARD)/auto.c option_table.h " + action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" end makerule ./auto.inc - depends "./romcc ./auto.E" - action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" -# action "./romcc -O2 ./auto.E > auto.inc" + depends "./auto.E ./romcc" + action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc" end -mainboardinit cpu/p6/enable_mmx_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/p6/disable_mmx_sse.inc -# + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + ### -### Include the secondary Configuration files +### O.k. We aren't just an intermediary anymore! ### +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 config chip.h +# sample config for tyan/s2735 chip northbridge/intel/e7501 - device pci_domain 0 - device pci 0.0 on end - device pci 0.1 on end - device pci 2.0 on - chip southbridge/intel/i82870 - device pci 1c.0 - device pci 1d.0 - device pci 1e.0 - device pci 1f.0 - end - end - device pci 6.0 on end - chip southbridge/intel/i82801er - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - device pci 1e.0 on end - device pci 1f.0 on - # device pci 8.0 end - chip winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - end - end - end - device pci 1f.1 off end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.5 off end - device pci 1f.6 off end - - end - end - device apic_cluster 0 - chip cpu/intel/socket_mPGA604_533Mhz - apic 0 - end - chip cpu/intel/socket_mPGA604_533Mhz - apic 6 - end - end + device pci_domain 0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 2.0 on + chip southbridge/intel/i82870 + device pci 1c.0 on end + device pci 1d.0 on end + device pci 1e.0 on end + device pci 1f.0 on end + end + end + device pci 6.0 on end + chip southbridge/intel/i82801er + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + device pci 1e.0 on end + device pci 1f.0 on + # device pci 8.0 end + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + end + end + end + device pci 1f.1 off end + device pci 1f.2 on end + device pci 1f.3 on end + device pci 1f.5 off end + device pci 1f.6 off end + + end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604_533Mhz + device apic 0 on end + end + chip cpu/intel/socket_mPGA604_533Mhz + device apic 6 on end + end + end end -dir /pc80 -#dir /bioscall diff --git a/src/mainboard/tyan/s2735/auto.c b/src/mainboard/tyan/s2735/auto.c index 3a99aa29a9..c2e59285fb 100644 --- a/src/mainboard/tyan/s2735/auto.c +++ b/src/mainboard/tyan/s2735/auto.c @@ -1,10 +1,12 @@ #define ASSEMBLY 1 + #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> -#include <arch/smp/lapic.h> +#include <cpu/x86/lapic.h> +#include <arch/cpu.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -12,17 +14,13 @@ #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" - -#if 1 -#include "cpu/p6/apic_timer.c" +#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - -#include "cpu/p6/boot_cpu.c" +#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/debug.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" - -#include "cpu/p6/earlymtrr.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -55,7 +53,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7501/reset_test.c" #include "sdram/generic_sdram.c" -static void main(void) +static void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -66,14 +64,21 @@ static void main(void) }, }; -#if 1 - enable_lapic(); - init_timer(); -#endif - + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + early_mtrr_init(); + enable_lapic(); + init_timer(); + + } + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + // setup_default_resource_map(); #if 0 print_pci_devices(); diff --git a/src/mainboard/tyan/s2735/chip.h b/src/mainboard/tyan/s2735/chip.h index bdde8a6df5..d63c156af5 100644 --- a/src/mainboard/tyan/s2735/chip.h +++ b/src/mainboard/tyan/s2735/chip.h @@ -1,4 +1,4 @@ -extern struct chip_operations mainboard_tyan_s2735_control; +extern struct chip_operations mainboard_tyan_s2735_ops; struct mainboard_tyan_s2735_config { int fixup_scsi; diff --git a/src/mainboard/tyan/s2735/failover.c b/src/mainboard/tyan/s2735/failover.c index 6ba3cae62a..91cd69317c 100644 --- a/src/mainboard/tyan/s2735/failover.c +++ b/src/mainboard/tyan/s2735/failover.c @@ -4,22 +4,14 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <arch/romcc_io.h> -#include <arch/smp/lapic.h> +#include <cpu/x86/lapic.h> #include "pc80/mc146818rtc_early.c" #include "southbridge/intel/i82801er/cmos_failover.c" -#include "cpu/p6/boot_cpu.c" +#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/reset_test.c" -#define HAVE_REGPARM_SUPPORT 0 -#if HAVE_REGPARM_SUPPORT static unsigned long main(unsigned long bist) { -#else -static void main(void) -{ - unsigned long bist = 0; - -#endif /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { goto normal_image; @@ -51,9 +43,5 @@ static void main(void) ); #endif fallback_image: -#if HAVE_REGPARM_SUPPORT return bist; -#else - return; -#endif } diff --git a/src/mainboard/tyan/s2735/mainboard.c b/src/mainboard/tyan/s2735/mainboard.c index 2531a701d9..ccc3a93b27 100644 --- a/src/mainboard/tyan/s2735/mainboard.c +++ b/src/mainboard/tyan/s2735/mainboard.c @@ -139,10 +139,10 @@ static struct device_operations mainboard_operations = { static void enable_dev(device_t dev) { - dev->ops = &mainboard_ops; + dev->ops = &mainboard_operations; } -struct chip_operations mainboard_tyan_s2735_control = { +struct chip_operations mainboard_tyan_s2735_ops = { .enable_dev = enable_dev, .name = "Tyan s2735 mainboard ", }; diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 25b1929eba..35baeb31ce 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -4,7 +4,7 @@ #include <string.h> #include <stdint.h> -void *smp_write_config_table(void *v, unsigned long * processor_map) +void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "TYAN "; @@ -28,7 +28,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) mc->mpe_checksum = 0; mc->reserved = 0; - smp_write_processors(mc, processor_map); + smp_write_processors(mc); /*Bus: Bus ID Type*/ @@ -41,19 +41,21 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 8, 0x20, 0xfec00000); { - struct pci_dev *dev; - uint32_t base; + device_t dev; + struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - base &= PCI_BASE_ADDRESS_MEM_MASK; - smp_write_ioapic(mc, 9, 0x20, base); + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x09, 0x20, res->base); + } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - base &= PCI_BASE_ADDRESS_MEM_MASK; - smp_write_ioapic(mc, 0xa, 0x20, base); + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x0a, 0x20, res->base); + } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# @@ -157,9 +159,9 @@ Compatibility Bus Address return smp_next_mpe_entry(mc); } -unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map) +unsigned long write_smp_table(unsigned long addr) { void *v; v = smp_write_floating_table(addr); - return (unsigned long)smp_write_config_table(v, processor_map); + return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb index 6aa9778a12..da285a5f6a 100644 --- a/src/mainboard/tyan/s4880/Options.lb +++ b/src/mainboard/tyan/s4880/Options.lb @@ -105,7 +105,7 @@ default LB_CKS_LOC=123 ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_CPUS=4 ## ## Build code to setup a generic IOAPIC diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb index 0462ee4ec7..948f71ea85 100644 --- a/src/mainboard/tyan/s4882/Options.lb +++ b/src/mainboard/tyan/s4882/Options.lb @@ -105,7 +105,7 @@ default LB_CKS_LOC=123 ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_CPUS=4 ## ## Build code to setup a generic IOAPIC diff --git a/targets/tyan/s2735/Config.lb b/targets/tyan/s2735/Config.lb index 7a3faf4f9c..1319482edf 100644 --- a/targets/tyan/s2735/Config.lb +++ b/targets/tyan/s2735/Config.lb @@ -1,265 +1,43 @@ # Sample config file for -# the Tyan s2735 +# the Tyan s2735 # This will make a target directory of ./s2735 -loadoptions - target s2735 +mainboard tyan/s2735 -uses ARCH -uses CONFIG_COMPRESS -uses CONFIG_IOAPIC -uses CONFIG_ROM_STREAM -uses CONFIG_ROM_STREAM_START -uses CONFIG_SMP -uses CONFIG_UDELAY_TSC -uses CPU_FIXUP -uses FALLBACK_SIZE -uses HAVE_FALLBACK_BOOT -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses i586 -uses i686 -uses INTEL_PPRO_MTRR -uses HEAP_SIZE -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -#uses MEMORY_HOLE -uses PAYLOAD_SIZE -uses _RAMBASE -uses _ROMBASE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_OFFSET -uses ROM_SECTION_SIZE -uses ROM_SIZE -uses STACK_SIZE -uses USE_FALLBACK_IMAGE -uses USE_OPTION_TABLE -uses HAVE_OPTION_TABLE -uses CONFIG_CHIP_CONFIGURE - -uses CONFIG_CONSOLE_BTEXT -uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -#SMDC Support -#uses CONFIG_CONSOLE_SERIAL8250_2 -#uses TTYS1_BAUD -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses DEBUG -uses CONFIG_MAX_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses LINUXBIOS_EXTRA_VERSION -uses XIP_ROM_SIZE -uses XIP_ROM_BASE - -uses CONFIG_FS_STREAM -uses CONFIG_IDE - -uses HAVE_HARD_RESET - -#uses CONFIG_VGABIOS -#uses CONFIG_REALMODE_IDT -#uses CONFIG_PCIBIOS -#uses VGABIOS_START -#uses SCSIFW_START - -# -#uses CONFIG_LSI_SCSI_FW_FIXUP - -option HAVE_OPTION_TABLE=1 -option HAVE_MP_TABLE=1 -option CPU_FIXUP=1 -option CONFIG_UDELAY_TSC=0 -option i686=1 -option i586=1 -option INTEL_PPRO_MTRR=1 -#option ROM_SIZE=524288 -option ROM_SIZE=1048576 - -option HAVE_HARD_RESET=1 - -#option CONFIG_CONSOLE_BTEXT=1 -#option CONFIG_VGABIOS=1 -#option CONFIG_REALMODE_IDT=1 -#option CONFIG_PCIBIOS=1 -#option VGABIOS_START=0xfff8c000 -#option SCSIFW_START=0xfff80000 - -#option CONFIG_FS_STREAM=1 -#option CONFIG_IDE=1 - -option HAVE_FALLBACK_BOOT=1 - -# use the new chip configure code. - -option CONFIG_CHIP_CONFIGURE=1 -#option CONFIG_LSI_SCSI_FW_FIXUP=1 - - -# -### -### Build code to export a programmable irq routing table -### -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=15 -# -### -### Build code for SMP support -### Only worry about 2 micro processors -### -option CONFIG_SMP=1 -option CONFIG_MAX_CPUS=4 -option CONFIG_LOGICAL_CPUS=1 -option CONFIG_MAX_PHYSICAL_CPUS=2 -# -### -### Build code to setup a generic IOAPIC -### -option CONFIG_IOAPIC=1 -# -### -### MEMORY_HOLE instructs earlymtrr.inc to -### enable caching from 0-640KB and to disable -### caching from 640KB-1MB using fixed MTRRs -### -### Enabling this option breaks SMP because secondary -### CPU identification depends on only variable MTRRs -### being enabled. -### -#option MEMORY_HOLE=0 -# -### -### Clean up the motherboard id strings -### -option MAINBOARD_PART_NUMBER="S2735" -option MAINBOARD_VENDOR="Tyan" -### -### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. -### -#option FALLBACK_SIZE=524288 -#option FALLBACK_SIZE=98304 -option FALLBACK_SIZE=131072 - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -option ROM_IMAGE_SIZE=65536 - - -### -### Compute where this copy of linuxBIOS will start in the boot rom -### -# -### - -## We do use compressed image -option CONFIG_COMPRESS=1 - -option CONFIG_CONSOLE_SERIAL8250=1 -option TTYS0_BAUD=115200 - -#SMDC support -#option CONFIG_CONSOLE_SERIAL8250_2=1 -#option TTYS1_BAUD=19200 - - -## -### Select the linuxBIOS loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -option DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -option MAXIMUM_CONSOLE_LOGLEVEL=8 - -option DEBUG=1 - -# - -## LinuxBIOS C code runs at this location in RAM -option _RAMBASE=0x004000 - -## -## Use a 32K stack -## -option STACK_SIZE=0x8000 - -## -## Use a 56K heap -## -option HEAP_SIZE=0xe000 - -# -### -### Compute the start location and size size of -### The linuxBIOS bootloader. -### -option CONFIG_ROM_STREAM = 1 - -# -# +# Tyan s2735 romimage "normal" -# 48K for SCSI FW +# 48K for SCSI FW # option ROM_SIZE = 475136 -# 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 +# 48K for SCSI FW and 48K for ATI ROM +# option ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" - option USE_FALLBACK_IMAGE=0 - option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - option ROM_SECTION_OFFSET= 0 - - option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE) - -# option XIP_ROM_SIZE = FALLBACK_SIZE - option XIP_ROM_SIZE = 65536 - option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) - - mainboard tyan/s2735 -# payload ../../../payloads/e1000--ide_disk.zelf +# option ROM_SIZE = 458752 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x10000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" +# payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf -# payload ../../../payloads/filo_mem_btext.elf -# payload ../../../payloads/filo_btext.zelf - payload ../../../payloads/e1000--filo_btext.zelf +# payload ../../../payloads/filo.zelf +# payload ../../../payloads/tg3--filo.zelf +# payload ../../../payloads/e1000--filo.zelf +# payload ../../../payloads/tg3--e1000--filo.zelf + payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end romimage "fallback" - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" option USE_FALLBACK_IMAGE=1 - option ROM_SECTION_SIZE = FALLBACK_SIZE - option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE) - - option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE) - -# option XIP_ROM_SIZE = FALLBACK_SIZE - option XIP_ROM_SIZE = 65536 - option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) - - mainboard tyan/s2735 -# payload ../../../payloads/e1000--ide_disk.zelf + option ROM_IMAGE_SIZE=0x10000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" +# payload ../../../payloads/tg3--ide_disk.zelf +# payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf -# payload ../../../payloads/filo_mem_btext.elf -# payload ../../../payloads/e1000_btext.zelf - payload ../../../payloads/e1000--filo_btext.zelf - +# payload ../../../payloads/filo.zelf +# payload ../../../payloads/tg3--filo.zelf +# payload ../../../payloads/e1000--filo.zelf +# payload ../../../payloads/tg3--e1000--filo.zelf + payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2735/ns2735 b/targets/tyan/s2735/ns2735 index f983eb4033..865d45aedf 100644 --- a/targets/tyan/s2735/ns2735 +++ b/targets/tyan/s2735/ns2735 @@ -1,5 +1,5 @@ #!/bin/bash -TYANMB=s27i35 +TYANMB=s2735 cd "$TYANMB" make #cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" |