diff options
| -rw-r--r-- | src/cpu/intel/haswell/haswell.h | 6 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 7 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cb602ceaa9..e45acd5a27 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -3,6 +3,7 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H +#include <arch/cpu.h> #include <stdint.h> /* CPU types without stepping */ @@ -168,6 +169,11 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); /* CPU identification */ +static inline u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + static inline int haswell_is_ult(void) { return CONFIG(INTEL_LYNXPOINT_LP); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9881bb880f..b1f8bba815 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -294,8 +294,11 @@ static void initialize_vr_config(void) msr = rdmsr(MSR_VR_MISC_CONFIG2); msr.lo &= ~0xffff; /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; + set the fast ramp voltage in 10mV steps. */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) + msr.lo |= 0x006a; /* 1.56V */ + else + msr.lo |= 0x006f; /* 1.60V */ wrmsr(MSR_VR_MISC_CONFIG2, msr); } |