diff options
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 9c179693ed..30377aaf79 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -135,6 +135,7 @@ struct soc_intel_tigerlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index b9dbec87f5..3fbb89a793 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -165,6 +165,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; + params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; } /* Enable ClkReqDetect for enabled port */ |