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diff --git a/Documentation/mainboard/apple/macbookair5_2.md b/Documentation/mainboard/apple/macbookair5_2.md new file mode 100644 index 0000000000..22b9bc765c --- /dev/null +++ b/Documentation/mainboard/apple/macbookair5_2.md @@ -0,0 +1,151 @@ +# Apple MacBook Air 5,2 + +This page describes how to run coreboot on MacBook Air 5,2, also known +as 13'' Mid 2012. + +```eval_rst ++-------------+-------------+ +| Model No. | Motherboard | ++=============+=============+ +| A1466 | 820-3209 | ++-------------+-------------+ +``` + +## RAM configurations + +This laptop comes with 6 different memory module variants. Not all of +them are supported at the moment. To determine which memory you have in your +MacBook Air 5,2, you can use inteltool and +[this script](https://github.com/gch1p/get_macbook_ramcfg). You need to run them +on the target machine. + +First, build inteltool: +```console +$ cd util/inteltool +$ make -j4 +``` +Download the script and make it executable. Then run: +```console +$ sudo ./inteltool -g | /path/to/get_macbook_ramcfg -m mba52 +``` + +You should get a name of RAM configuration installed in your MacBook. Use the +table below to determine if it's supported. +```eval_rst ++-------------------+-----------+ +| RAM configuration | Supported | ++===================+===========+ +| 4g_hynix | **Yes** | ++-------------------+-----------+ +| 8g_hynix | No | ++-------------------+-----------+ +| 4g_samsung | No | ++-------------------+-----------+ +| 8g_samsung | No | ++-------------------+-----------+ +| 4g_elpida | No | ++-------------------+-----------+ +| 8g_elpida | No | ++-------------------+-----------+ +``` +If your RAM configuration is not supported, you can help supporting it. Run +`sudo inteltool -m`, save output to a text file and send a message to coreboot +[mailing list](/community/forums.html) specifying your memory configuration name +with the text file attached. + +## Flashing instructions + +### External flashing + +The board has one 8 MiB flash chip. It's WSON-8 so using clip is not +possible. To access the chip, you need to remove the motherboard as +it's located on the bottom side of the board. + +The other way to access the flash chip is by using **J5100 debug port** +on the board and an **SPI adapter**. To access the port, remove the back +cover. + + + +To access SPI flash chip through the debug port, you need an adapter. +One of possible options is A4052 Chipmunk Easy Flash. To use this one, +you also need 8-pin JST-SH 1.0mm male cable that plugs into this adapter's +8-pin header on the other side. + + + +Connect the JST-SH cable's wires to your SPI programmer, **all except +VCC (3v3)**, then detach battery connector from the mainboard: + + + +Plug the adapter: + + + +The 3v3 pin of J5100 is not connected directly to the flash chip (U6100) +so it's not recommended to use it, as it's very unreliable and almost +never works. Instead, connect the 3v3 pin of your programmer to U7930's +3v3. It's wired directly to SPI chip: + + + + + +Probe the chip with flashrom. If everything is set up correctly, flashrom +should detect the chip: + +``` +flashrom v1.1 on Linux 4.14.24-v7+ (armv7l) +flashrom is free software, get the source code at https://flashrom.org + +Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). +Found Micron/Numonyx/ST flash chip "N25Q064..3E" (8192 kB, SPI) on linux_spi. +``` + +### Internal flashing + +See [here](/flash_tutorial/int_macbook.md) how to flash coreboot internally when +running Apple EFI. + +--- + +The flash layout of the OEM firmware is as follows: + +``` +00000000:00000fff fd +00190000:007fffff bios +00001000:0018ffff me +``` + +## Working + +- 4 GiB (Hynix RAM) model +- Linux 4.9, Linux 5.10 +- SeaBIOS +- GRUB +- Tianocore +- Wi-Fi +- S3 suspend and resume +- Both USB ports +- Trackpad +- libgfxinit +- me_cleaner +- Speakers +- ACPI support for battery, AC, lid (lid wakeup also works) +- SD card reader +- Camera +- Mic +- usbdebug (usb port on the left side) + +## Untested + +- Thunderbolt + +## Known issues + +- Bad sound in headphones. + +## TODOs +- Support other memory configurations +- Fix headphones diff --git a/Documentation/mainboard/apple/mba52_3v3.jpg b/Documentation/mainboard/apple/mba52_3v3.jpg Binary files differnew file mode 100644 index 0000000000..38e7ad75eb --- /dev/null +++ b/Documentation/mainboard/apple/mba52_3v3.jpg diff --git a/Documentation/mainboard/apple/mba52_3v3_2.jpg b/Documentation/mainboard/apple/mba52_3v3_2.jpg Binary files differnew file mode 100644 index 0000000000..c9ccf94cf3 --- /dev/null +++ b/Documentation/mainboard/apple/mba52_3v3_2.jpg diff --git a/Documentation/mainboard/apple/mba52_adapter.jpg b/Documentation/mainboard/apple/mba52_adapter.jpg Binary files differnew file mode 100644 index 0000000000..3733782521 --- /dev/null +++ b/Documentation/mainboard/apple/mba52_adapter.jpg diff --git a/Documentation/mainboard/apple/mba52_bat_unplug.jpg b/Documentation/mainboard/apple/mba52_bat_unplug.jpg Binary files differnew file mode 100644 index 0000000000..8488a6a647 --- /dev/null +++ b/Documentation/mainboard/apple/mba52_bat_unplug.jpg diff --git a/Documentation/mainboard/apple/mba52_motherboard.jpg b/Documentation/mainboard/apple/mba52_motherboard.jpg Binary files differnew file mode 100644 index 0000000000..b6bb46644b --- /dev/null +++ b/Documentation/mainboard/apple/mba52_motherboard.jpg diff --git a/Documentation/mainboard/apple/mba52_plug_j5100.jpg b/Documentation/mainboard/apple/mba52_plug_j5100.jpg Binary files differnew file mode 100644 index 0000000000..fbfe3d4247 --- /dev/null +++ b/Documentation/mainboard/apple/mba52_plug_j5100.jpg diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3260f73484..888a7a2687 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -9,6 +9,10 @@ This section contains documentation about coreboot on specific mainboards. ## AMD - [padmelon](amd/padmelon/padmelon.md) +## Apple + +- [MacBook Air 5,2](apple/macbookair5_2.md) + ## ASRock - [H81M-HDS](asrock/h81m-hds.md) diff --git a/src/mainboard/apple/macbookair5_2/Kconfig b/src/mainboard/apple/macbookair5_2/Kconfig new file mode 100644 index 0000000000..6ff51777e4 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/Kconfig @@ -0,0 +1,49 @@ +if BOARD_APPLE_MACBOOKAIR5_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select GFX_GMA_PANEL_1_ON_EDP + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select HAVE_SPD_IN_CBFS + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default apple/macbookair5_2 + +config MAINBOARD_PART_NUMBER + string + default "MacBookAir5,2" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 0 + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Apple Inc." + +endif diff --git a/src/mainboard/apple/macbookair5_2/Kconfig.name b/src/mainboard/apple/macbookair5_2/Kconfig.name new file mode 100644 index 0000000000..d8a1fbf85f --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKAIR5_2 + bool "MacBookAir5,2" diff --git a/src/mainboard/apple/macbookair5_2/Makefile.inc b/src/mainboard/apple/macbookair5_2/Makefile.inc new file mode 100644 index 0000000000..f525096f17 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/Makefile.inc @@ -0,0 +1,9 @@ +bootblock-y += gpio.c +bootblock-y += early_init.c + +romstage-y += gpio.c +romstage-y += early_init.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +subdirs-y += spd diff --git a/src/mainboard/apple/macbookair5_2/acpi/ec.asl b/src/mainboard/apple/macbookair5_2/acpi/ec.asl new file mode 100644 index 0000000000..75f766bdb9 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi/ec.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define LIDS_OFFSET 0x60 +#define HPAC_OFFSET 0x60 +#define WKLD_OFFSET 0x68 + +#include <ec/apple/acpi/ec.asl> +#include <ec/apple/acpi/ac.asl> +#include <ec/apple/acpi/lid.asl> diff --git a/src/mainboard/apple/macbookair5_2/acpi/platform.asl b/src/mainboard/apple/macbookair5_2/acpi/platform.asl new file mode 100644 index 0000000000..e913122bd5 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package(){0,0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/apple/macbookair5_2/acpi/superio.asl b/src/mainboard/apple/macbookair5_2/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi/superio.asl diff --git a/src/mainboard/apple/macbookair5_2/acpi_tables.c b/src/mainboard/apple/macbookair5_2/acpi_tables.c new file mode 100644 index 0000000000..ad1295b6b3 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi_tables.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookair5_2/board_info.txt b/src/mainboard/apple/macbookair5_2/board_info.txt new file mode 100644 index 0000000000..15e31f43c6 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: y +ROM package: WSON-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookair5_2/cmos.default b/src/mainboard/apple/macbookair5_2/cmos.default new file mode 100644 index 0000000000..e4d037ae5d --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +gfx_uma_size=32M +me_state=Normal diff --git a/src/mainboard/apple/macbookair5_2/cmos.layout b/src/mainboard/apple/macbookair5_2/cmos.layout new file mode 100644 index 0000000000..a71d9d0f80 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/cmos.layout @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: ME +425 1 e 13 me_state +426 2 h 0 me_state_prev + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- +enumerations +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +13 0 Normal +13 1 Disabled + +# ----------------------------------------------------------------- +checksums +checksum 392 447 984 diff --git a/src/mainboard/apple/macbookair5_2/devicetree.cb b/src/mainboard/apple/macbookair5_2/devicetree.cb new file mode 100644 index 0000000000..10bddf1226 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/devicetree.cb @@ -0,0 +1,74 @@ +chip northbridge/intel/sandybridge + register "gfx.ndid" = "2" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000710" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "1" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "10" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "740" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x07100710" + register "pci_mmio_size" = "2048" + + device cpu_cluster 0 on + chip cpu/intel/model_206ax + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x106b 0x00fe + end + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00fe + end + + subsystemid 0x8086 0x7270 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/apple/macbookair5_2/dsdt.asl b/src/mainboard/apple/macbookair5_2/dsdt.asl new file mode 100644 index 0000000000..fe72d28be0 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookair5_2/early_init.c b/src/mainboard/apple/macbookair5_2/early_init.c new file mode 100644 index 0000000000..c4c060b671 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/early_init.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <cbfs.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* Ext A (XHCI/EHCI) */ + { 1, 0, 1 }, /* Ext B (XHCI) */ + { 1, 0, 2 }, /* Ext C (XHCI/EHCI) */ + { 1, 0, 3 }, /* Ext D (XHCI) */ + { 0, 0, -1 }, /* Unused */ + { 1, 0, -1 }, /* SD */ + { 1, 0, -1 }, /* Wi-Fi */ + { 1, 0, -1 }, /* USB Hub (All LS/FS Devices) */ + { 1, 0, -1 }, /* Camera */ + { 1, 0, 4 }, /* Ext B (EHCI) */ + { 1, 0, 5 }, /* Ext D (EHCI) */ + { 1, 0, -1 }, /* BT */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ +}; + +static uint8_t *get_spd_data(int spd_index) +{ + uint8_t *spd_file; + size_t spd_file_len; + printk(BIOS_DEBUG, "spd index %d\n", spd_index); + spd_file = cbfs_map("spd.bin", &spd_file_len); + if (!spd_file) + die("SPD data not found."); + if (spd_file_len < spd_index * 256) + die("Missing SPD data."); + return spd_file + spd_index * 256; +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + uint8_t *memory; + const int spd_gpio_vector[] = {71, 70, 69, 68, -1}; + int ramcfg = get_gpios(spd_gpio_vector); + int spd_index = -1; + + /* + * GPIO68 GPIO69 GPIO70 GPIO71 Memory Supported + * 0 0 0 0 4 GiB Hynix Yes + * 0 1 0 0 8 GiB Hynix No + * 0 0 1 0 4 GiB Samsung No + * 0 1 1 0 8 GiB Samsung No + * 0 1 1 1 8 GiB Elpida No + * 0 0 1 1 4 GiB Elpida No + */ + + if (ramcfg == 0) + spd_index = 0; + + if (spd_index == -1) + die("Unsupported memory, RAMCFG=%d\n", ramcfg); + + memory = get_spd_data(spd_index); + memcpy(&spd[0], memory, 256); + memcpy(&spd[2], memory, 256); +} diff --git a/src/mainboard/apple/macbookair5_2/gma-mainboard.ads b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads new file mode 100644 index 0000000000..0cf02cd3b2 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookair5_2/gpio.c b/src/mainboard/apple/macbookair5_2/gpio.c new file mode 100644 index 0000000000..8582442879 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/gpio.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookair5_2/hda_verb.c b/src/mainboard/apple/macbookair5_2/hda_verb.c new file mode 100644 index 0000000000..7650b131ce --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/hda_verb.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus CS4206 */ + 0x106b5600, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0, 0x106b5600), + AZALIA_PIN_CFG(0, 0x09, 0x0e2b4030), + AZALIA_PIN_CFG(0, 0x0a, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x90100120), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90a00110), + AZALIA_PIN_CFG(0, 0x0e, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x10, 0x400000f0), + AZALIA_PIN_CFG(0, 0x12, 0x400000f0), + AZALIA_PIN_CFG(0, 0x15, 0x400000f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 4, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560010), + AZALIA_PIN_CFG(3, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = { + 0x00270500, /* Set PS to D0 on DAC1 */ + 0x00470500, /* Set PS to D0 on DAC3 */ + 0x00270650, /* Set converter stream on DAC1 */ + 0x00470650, /* Set converted stream on DAC3 */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookair5_2/mainboard.c b/src/mainboard/apple/macbookair5_2/mainboard.c new file mode 100644 index 0000000000..d1bb64bbf9 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookair5_2/spd/4g_hynix.spd.hex b/src/mainboard/apple/macbookair5_2/spd/4g_hynix.spd.hex new file mode 100644 index 0000000000..667ac3d2ad --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/spd/4g_hynix.spd.hex @@ -0,0 +1,16 @@ +92 11 0b 03 03 00 00 01 03 52 01 08 0a 00 80 00 +6e 78 6e 32 6e 11 18 81 00 05 3c 3c 00 f0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc 2a +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/apple/macbookair5_2/spd/Makefile.inc b/src/mainboard/apple/macbookair5_2/spd/Makefile.inc new file mode 100644 index 0000000000..61ff1b71fe --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/spd/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = 4g_hynix # 0b0000 |
